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An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

TitleAn Integral Path Self-Calibration Scheme for a Dual-Loop PLL
Publication TypeJournal Article
Year of Publication2013
AuthorsFerriss, M. A., J-O. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, J. A. Tierno, A. Babakhani, S. Yaldiz, A. Valdes-Garcia, B. Sadhu, and D. Friedman
JournalIEEE Journal of Solid-State Circuits
Pagination996 - 1008
Date Published04/2013

An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of ${-}$126.5 dBc/Hz at 20.1 GHz and ${-}$ 124.2 dBc/Hz at 24 GHz.

Short TitleIEEE J. Solid-State Circuits