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A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

TitleA 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
Publication TypeConference Paper
Year of Publication2012
AuthorsPlouchart, J. - O., M. A. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, and D. Friedman
Conference NameIEEE Custom Integrated Circuits Conference - CICC 2012
Pagination1 - 4
Date Published09/2012
PublisherIEEE
Conference LocationSan Jose, CA
ISBN Number978-1-4673-1554-8
Abstract

A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5° RMS across all frequency bands.

DOI10.1109/CICC.2012.6330593