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A 21.8–27.5GHz PLL in 32nm SOI using Gm linearization to achieve −130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier

TitleA 21.8–27.5GHz PLL in 32nm SOI using Gm linearization to achieve −130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
Publication TypeConference Paper
Year of Publication2012
AuthorsSadhu, B., M. A. Ferriss, J-O. Plouchart, A. Natarajan, A. Rylyakov, A. Valdes-Garcia, B. D. Parker, S. Reynolds, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, J. Tierno, and D. Friedman
Conference NameIEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Pagination75 - 78
Date Published06/2012
PublisherIEEE
Conference LocationMontreal, QC, Canada
ISBN Number978-1-4673-0415-3
Keywords60GHz, phase noise, PLL, transconducance linearization, tuning range, VCO
Abstract

This paper describes a new approach to low phase noise LC VCO design based on transconductance linearization of the active devices. A prototype 25GHz VCO based on this approach is integrated in a dual loop PLL and achieves superior performance compared to the state of the art. The design is implemented in the 32nm SOI deep sub-micron CMOS technology and achieves a phase noise of -130dBc/Hz at 10MHz offset from a 22GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 500 measurements across PVT variations validate the proposed PLL design: phase noise variation across 46 dies for 3 different frequencies is σ <; 0.6dB, across supply variation over 0.7-1.5V is 2dB and across 80°C temperature variation is 2dB. At the 25GHz center frequency, the VCO FOMT is 188dBc/Hz.

DOI10.1109/RFIC.2012.6242235