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An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS

TitleAn integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS
Publication TypeConference Paper
Year of Publication2012
AuthorsFerriss, M. A., J-O. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, S. Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno, and D. Friedman
Conference Name2012 IEEE Symposium on VLSI Circuits2012 Symposium on VLSI Circuits (VLSIC)
Pagination176 - 177
Date Published06/2012
PublisherIEEE
Conference LocationHonolulu, HI
ISBN Number978-1-4673-0845-8
Abstract

A bandwidth self-calibration scheme is introduced as part of a 20.1GHz to 26.7GHz, low noise PLL in 32nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4dB to 1dB, when measured at 70 sites on a 300mm wafer. The PLL has a measured phase noise @10MHz offset of -126.5dBc/Hz at 20.1GHz.

DOI10.1109/VLSIC.2012.6243847