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A 60GHz variable-gain LNA in 65nm CMOS

TitleA 60GHz variable-gain LNA in 65nm CMOS
Publication TypeConference Paper
Year of Publication2008
AuthorsNatarajan, A., S. Nicolson, M-D. Tsai, and B. Floyd
Conference NameIEEE Asian Solid-State Circuits Conference (A-SSCC)
Pagination117 - 120
Date Published11/2008
Conference LocationFukuoka, Japan
ISBN Number978-1-4244-2604-1

A four-stage 60 GHz low-noise amplifier is implemented in 65 nm CMOS with nMOS f<sub>t</sub> of 210 GHz. The LNA incorporates a reflection-type attenuator to provide variable gain with improved linearity in low-gain mode and a tunable notch filter for image rejection. The LNA, which consists of two common-source stages followed by two cascode stages, consumes 30.8 mW and achieves 5.9 dB NF and 15 dB gain at 60 GHz. The variable attenuator provides 10 dB of gain variation with the input-referred 1 dB compression point of the LNA being -15.1 dBm in high gain mode and -6 dBm in the low-gain mode. Each tunable notch filter stage provides an additional 8 dB attenuation of 37 GHz image signals, with the four-stage LNA achieving more than 35 dB image-rejection.