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Teraohm on-chip resistance realisation using switched capacitor topologies

TitleTeraohm on-chip resistance realisation using switched capacitor topologies
Publication TypeJournal Article
Year of Publication2012
AuthorsLi, W., T. Wang, J. Cao, and G. C. Temes
JournalElectronics Letters
Volume48
Issue11
Pagination623
Date Published05/2012
ISSN00135194
Abstract

Two large-resistance realisation schemes are proposed using switched-capacitor circuits. The equivalent resistance of the array realisation increases as the third power of the number of capacitor pairs, and that of the ladder realisation increases exponentially. The equivalent resistance for the ladder scheme also grows with the capacitance ratio. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area. Simulation results show that very low pole frequency (~9 Hz in the example) can be achieved with practical element values, and with a capacitance spread of only 10 in a three-stage ladder.

DOI10.1049/el.2012.0767
Short TitleElectron. Lett.