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A framework for assessing amorphous oxide semiconductor thin-film transistor passivation

TitleA framework for assessing amorphous oxide semiconductor thin-film transistor passivation
Publication TypeJournal Article
Year of Publication2012
AuthorsWager, J. F., K. Hoshino, E. S. Sundholm, R. E. Presley, R. Ravichandran, C. C. Knutson, D. A. Keszler, R. L. Hoffman, D. A. Mourey, and J. Robertson
JournalJournal of the Society for Information Display
Volume20
Issue10
Pagination589 - 595
Date Published10/2012
Abstract

Amorphous oxide semiconductor thin-film transistors (TFTs) are moving towards commercialization for a variety of display applications. Invariably, display applications require a bottom-gate TFT configuration in which passivation of the top channel layer surface is required. The objective of this work is to propose a conceptual model framework for assessing TFT passivation schemes, within the context of amorphous oxide semiconductor electronics. This model involves first estimating the energy of the charge neutrality levels (CNLs) for the channel and passivation layers. Then, an energy band diagram is drawn to establish the relative position of these CNLs prior to their establishment of intimate contact. A situation in which the passivation layer CNL is below that of the channel layer CNL is considered undesirable because interface state electronic transfer from the channel to the passivation layer leads to formation of an accumulation layer at this interface. Although the opposite case in which the passivation layer CNL is above that of the channel layer CNL is more desirable, the ideal situation would be when both CNLs align because no interface state electronic transfer would occur. This framework is then employed in a discussion of the passivation of indium gallium zinc oxide and zinc tin oxide bottom-gate TFTs.

Notes

Best paper of 2012 for the Journal of Information Display

DOI10.1002/jsid.120
Short TitleJnl Soc Info Display