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Efficient modeling of metal fill parasitic capacitance in on-chip transmission lines

TitleEfficient modeling of metal fill parasitic capacitance in on-chip transmission lines
Publication TypeConference Paper
Year of Publication2012
AuthorsShilimkar, V. S., S. G. Gaskill, and A. Weisshaar
Conference NameIEEE/MTT-S International Microwave Symposium - MTT 2012
Pagination1 - 3
Date Published06/2012
PublisherIEEE
Conference LocationMontreal, QC, Canada
ISBN Number978-1-4673-1086-4
Keywordscapacitance modeling, eddy-current loss, metal fill, on-chip transmission line
Abstract

We present a general modeling methodology for metal fill parasitic capacitance in on-chip transmission lines. Our approach is based on reducing the problem complexity in all three dimensions. Typical speed-up is 16 fold. The maximum error in self and mutual capacitance is < 6 % and < 10 %, respectively over a wide range of parameters. The agreement with measurements is within 2.1 %. We predict the slow-wave factor of transmission line designs with < 1.2 % error and Q degradation with < 4 % error.

DOI10.1109/MWSYM.2012.6259749