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A 10-b Ternary SAR ADC With Quantization Time Information Utilization

TitleA 10-b Ternary SAR ADC With Quantization Time Information Utilization
Publication TypeJournal Article
Year of Publication2012
AuthorsGuerber, J., H. Venkatram, M. Gande, A. Waters, and U. Moon
JournalIEEE Journal of Solid-State Circuits
Volume47
Issue11
Pagination2604 - 2613
Date Published11/2012
ISSN1558-173X
Abstract

The design of a ternary successive approximation (TSAR) analog-to-digital converter (ADC) with quantization time information utilization is proposed. The TSAR examines the transient information of a typical dynamic SAR voltage comparator to provide accuracy, speed, and power benefits. Full half-bit redundancy is shown, allowing for residue shaping which provides an additional 6 dB of signal-to-quantization-noise ratio (SQNR). Synchronous quantizer speed enhancements allow for a shorter worst case conversion time. An increased monotonicity switching algorithm, stage skipping due to reference grouping, and SAR logic modifications minimize overall dynamic energy. The architecture has been shown to reduce capacitor array switching power consumption and digital-to-analog converter (DAC) driver power by about 60% in a mismatch limited SAR, reduce comparator activity by about 20%, and require only 8.03 average comparisons and 6.53 average DAC movements for a 10-b ADC output word. A prototype is fabricated in 0.13-μm CMOS employing on-chip statistical time reference calibration, supply variability from 0.8 to 1.2 V, and small input signal power scaling. The chip consumes 84 μ W at 8 MHz with an effective number of bits of 9.3 for a figure of merit of 16.9 fJ/C-S for the 10-b prototype and 10.0 fJ/C-S for a 12-b enhanced prototype chip.

DOI10.1109/JSSC.2012.2211696
Short TitleIEEE J. Solid-State Circuits