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A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADC

TitleA 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADC
Publication TypeConference Paper
Year of Publication2012
AuthorsOh, T., N. Maghari, and U. Moon
Conference Name2012 Symposium on VLSI Circuits (VLSIC)
Pagination162 - 163
Date Published06/2012
PublisherIEEE
Conference LocationHonolulu, HI
ISBN Number978-1-4673-0845-8
Abstract

In this paper, a new ΔΣ ADC using a noise-shaped two-step integrating quantizer is presented. Attaining an extra order of noise-shaping from the integrating quantizer, the proposed ΔΣ ADC manifests a second-order noise-shaping with a first-order loop filter. Furthermore, this quantizer provides an 8b quantization in itself, drastically reducing the oversampling requirement. The proposed ADC also incorporates a new feedback DAC topology that alleviates feedback DAC complexity of a two-step 8b quantizer. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 70.7dB at 8.1mW power, with an 8x OSR at 80MHz sampling frequency.

DOI10.1109/VLSIC.2012.6243840