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A 71dB dynamic range third-order ΔΣ TDC using charge-pump

TitleA 71dB dynamic range third-order ΔΣ TDC using charge-pump
Publication TypeConference Paper
Year of Publication2012
AuthorsGande, M., N. Maghari, T. Oh, and U. Moon
Conference Name2012 Symposium on VLSI Circuits (VLSIC)
Pagination168 - 169
Date Published06/2012
PublisherIEEE
Conference LocationHonolulu, HI
ISBN Number978-1-4673-0845-8
Abstract

A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture combines the principles of noise-shaping quantization and charge-pump to build a third-order ΔΣ TDC with a dedicated feedback DAC. Fabricated in a 0.13μm CMOS process, the prototype TDC achieves better than 71dB DR and 67dB SNDR in 2.81MHz signal bandwidth (OSR=16) and consumes 2.58mW.

DOI10.1109/VLSIC.2012.6243843