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Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors

TitleConstant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors
Publication TypeJournal Article
Year of Publication2009
AuthorsHoshino, K., D. Hong, H. Q. Chiang, and J. F. Wager
JournalIEEE Transactions on Electron Devices
Volume56
Issue7
Pagination1365 - 1370
Date Published05/2009
ISSN0018-9383
Keywordsamorphous oxide semiconductor (AOS), gallium compounds, indium compound, indium–gallium–zinc oxide, stability, thin-film transistors, zinc compounds
Abstract

Constant-voltage-bias (VDS = VGS = 30 V) stress measurements are performed for a period of 105⁵ s on thin-film transistors (TFTs) with amorphous indium-gallium-zinc-oxide (IGZO) channel layers fabricated via RF sputtering using a postdeposition annealing temperature of 200degC, 250degC, or 300degC. Thermal silicon dioxide is employed as a TFT bottom-gate insulator. All SiO₂/IGZO TFTs tested exhibit the following: 1) a positive rigid log(ID)- VGS transfer curve shift; 2) a continuous drain-current decrease over the entire stress duration; and 3) recovery of the log(ID)-VGS transfer curve toward the prestressed state when the stressed TFT is left unbiased in the dark at room temperature for an extended period of time. The SiO₂/IGZO TFTs subjected to a higher postdeposition annealing temperature are more stable. A small (and typically negligible) amount of clockwise hysteresis is present in the log(ID) -VGS transfer curves of IGZO TFTs. These instability and hysteresis observations are consistent with a SiO₂/ IGZO TFT instability mechanism involving electron trapping within the IGZO channel layer.

DOI10.1109/TED.2009.2021339
Short TitleIEEE Trans. Electron Devices