Trapping of interface electrons in InP metal/insulator/semiconductor field effect transistors (MISFETs) has previously been reported. The rate of trapping appears to be strongly dependent on the fabrication process although the cause of the trap states is not presently known. In this paper a model for the cause of the traps is proposed based upon a review of the InP MIS literature and knowledge of the chemical composition of the InP native oxide. The model associates the traps with the presence of In₂O₃ near the insulator-InP interface. The In₂O₃ is formed either by oxidation of the InP surface or by a reaction between the InPO₄ native oxide and the depositing insulator. A number of assumptions have been made in order to fit the In₂O₃ trap model to the reported MISFET measurements. Thus, at this point the model should not be considered complete but a basis for further experiments.