The bias stability of zinc-tin-oxide (ZTO) thin-film transistors (TFTs) with either Al₂O₃ gate dielectrics deposited via atomic layer deposition (ALD) or SiO₂ gate dielectrics deposited via plasma-enhanced chemical vapor deposition (PECVD) was compared. Both device types showed incremental mobility ≥ 11 cm²/V s, subthreshold slopes <0.4 V/dec, and ION/IOFF ratios of ∼ 10⁷. During repeated ID-VGS sweeping, both device types showed positive parallel shift of the turn-on voltage (VON) without significant degradation of subthreshold slope or mobility, consistent with electron trapping without creation of new traps. A smaller VON shift was observed in the SiO₂/ZTO devices. In an effort to improve the bias stress stability of the Al₂O₃/ZTO devices, the impact of ALD temperature, plasma exposure of the Al₂O₃, and the addition of an interfacial PECVD SiO₂ capping layer were investigated. The positive bias stress stability of the Al₂O₃/ZTO TFTs was found to be relatively unaffected by the Al₂O₃ ALD temperature, degraded with plasma exposure, and improved by the addition of a thin ( ∼ 3 nm) PECVD SiO₂ interfacial layer between the Al₂O₃ dielectric and the ZTO channel. These results point to the vicinity of the Al₂O₃/ZTO interface as the dominant source of charge trapping.