OREGON STATE UNIVERSITY

You are here

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

Title74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain
Publication TypeJournal Article
Year of Publication2009
AuthorsMaghari, N., S. Kwon, and U. Moon
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue8
Pagination2212 - 2221
Date Published08/2009
ISSN0018-9200
KeywordsCMOS analog integrated circuits, delta-sigma modulation, switched-capacitor circuits
Abstract

This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop modulators. Enabling the use of low gain opamps also allows low-voltage operation due to the reduced number of transistors between the power supply rails. In addition, all the digital filters are removed from the output of this modulator to minimize the overall system requirement. Instead, an in-loop digital addition facilitates the desired noise transfer functions of both loops. This combines stability advantage of the multi-loop structure with relaxed circuit requirement of the single-loop modulator. A fourth order modulator is implemented in a 0.18 mum CMOS technology to demonstrate this concept. Measurement results show that, with open-loop opamp gain of less than 35 dB, the implemented prototype IC achieves over 74 dB SNDR at an oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW at 1.2 V supply.

DOI10.1109/JSSC.2009.2022302
Short TitleIEEE J. Solid-State Circuits