Sponsored by:
IEEE TCCA, IEEE TCPP, ACM SIGARCH, & IFIP Working Group 10.3
& Generous Corporate Support from
Intel, SGI, & IBM
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Keynote Speaker: Fred Pollack, Intel Corporation
Title: New Challenges in Micro-architecture and Compiler Design
Abstract: Through a combination silicon process technology and microarchitecture innovation, microprocessor performance has been doubling every 18 months for the last 25 years. This can continue for at least the next 10 years, but not following the same path as the last 25. We have challenges in scaling the silicon technology, e.g., in power and signaling. We have challenges in scaling microarchitecture, e.g., how much parallelism can we extract from a single thread. Neither hardware nor software alone can solve all the issues in these new challenges. More synergy between microarchitecture and compiler is necessary. This talk will discuss some of the new microarchitecture and compiler directions, in particular, on thread-level parallelism and dynamic compilation/optimization.
Bio: Fred Pollack is the Director of the Microprocessor Research Labs (MRL, http://intel.com/research/mrl), with labs in California, Oregon, Israel, China, and Russia. MRL focuses in several different areas including computer architecture, compilers, circuits, graphics, video, vision, security, and new computing models. From mid-1992 to early 1999, Fred was director of the MAP group in MPG. This division is responsible for all Intel platform architecture and performance analysis. In this role, he was also responsible for directing the planning of Intel's future microprocessors. From mid-1990 to mid-1992, he was the Architecture Manager for the Pentium Pro microprocessor. He joined Intel in 1978. Earlier assignments included manager of the i960 architecture and chief architect for an advanced object-oriented, distributed operating system. In January of 1993, he was named an Intel Fellow.
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