Patrick Chiang

Associate Professor
Electrical & Computer Engineering
Education: 
  • University of California - Berkeley,  B.S. Degree, 1998, Electrical Engineering
  • Stanford University, M.S. Degree, 2001, Electrical Engineering
  • Stanford University, Ph.D., 2007, Electrical Engineering
Biography: 

Patrick Chiang received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 2001 and 2007.

In 1998, he was with Datapath Systems (now LSI Logic), working on analog front-ends for DSL chipsets. In 2002 he was a research intern at Velio Communications (now Rambus) working on 10GHz clock synthesis architectures. In 2004 he was a consultant at startup Telegent Systems, evaluating low phase noise VCOs for CMOS mobile TV tuners. In 2006 he was a visiting NSF postdoctoral researcher at Tsinghua University, China, investigating low power, low voltage RF transceivers. In 2009 he was a visiting senior researcher at the ASIC State & Key Laboratory in Fudan University, Shanghai, China.

His interests are: 1) The design of energy-efficient, CMOS interconnects (on-chip/off-chip/wireless) — Energy-efficient interfaces will soon be a dominant portion of the power budget on future microprocessors and SoCs. These include on-chip links, off-chip multi-gigahertz I/O, and wireless data transmission. We are investigating new techniques in advanced CMOS processes to enable improved energy-efficiency (pJ/bit-transferred).

2) Wireless, wearable medical sensors — Advances in semiconductor technology will soon enable “bandaid-size” medical sensors, non-invasively attached to the human body, allowing for non-invasive monitoring of human activity. These sensors will capture measurement of minute electrical signals (i.e. brain-EEG signals, heart-ECG waves, accelerometer-based activity monitoring), which will provide continuous monitoring of medical condition, such as disease onset, vitamin/drug efficacy, sleep diagnosis, and brain cognition.

Research Interests: 

Research Areas
Energy-efficient CMOS interconnects (gigahertz ADCs, wireline on/off chip I/O, wireless); Wireless medical electronics

2011
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Xia, L., K. Shao, H. Chen, Y. Huang, Z. Hong, and P. Y. Chiang, "0.15-nJ/b 3–5-GHz IR-UWB System With Spectrum Tunable Transmitter and Merged-Correlator Noncoherent Receiver", IEEE Transactions on Microwave Theory and Techniques, vol. 59, issue 4, pp. 1147 - 1156, 04/2011. Abstract
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Moezzi-Madani, N., T. Thorolfsson, J. Crop, P. Y. Chiang, and W. R. Davis, "An energy-efficient 64-QAM MIMO detector for emerging wireless standards", 2011 Design, Automation & Test in Europe, Grenoble, France, IEEE, pp. 1 - 6, 03/2011. Abstract
Redfield, S., S. Woracheewan, H. Liu, P. Y. Chiang, J. Nejedlo, and R. Khanna, "Understanding the Ultrawideband Channel Characteristics Within a Computer Chassis", IEEE Antennas and Wireless Propagation Letters, vol. 10, pp. 191 - 194, 03/2011. Abstract
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Xia, L., S. Redfield, and P. Y. Chiang, "Experimental Characterization of a UWB Channel for Body Area Networks", EURASIP Journal on Wireless Communications and Networking, vol. 2011, pp. 1 - 11, 01/2011. Abstract
2010
Krishna, T., J. Postman, C. Edmonds, L. - S. Peh, and P. Y. Chiang, "SWIFT: A SWing-Reduced Interconnect for a Token-Based Network-on-Chip in 90nm CMOS", 2010 IEEE International Conference on Computer Design (ICCD 2010), Amsterdam, Netherlands, IEEE, pp. 439 - 446, 10/2010. Abstract
Jiang, T., W. Liu, F. Y. Zhong, C. Zhong, and P. Y. Chiang, "Single-Channel, 1.25-GS/s, 6-Bit, Loop-Unrolled Asynchronous SAR-ADC in 40nm-CMOS", 2010 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 1 - 4, 09/2010. Abstract
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Chiang, P. Y., and C. Hu, "Chaotic Pulse-Position Baseband Modulation for an Ultra-Wideband Transceiver in CMOS", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, issue 8, pp. 642 - 646, 08/2010. Abstract
Hu, C., P. Y. Chiang, K. Hu, H. Liu, R. Khanna, and J. Nejedlo, "A 90nm-CMOS, 500Mbps, Fully-Integrated IR-UWB Transceiver Using Pulse Injection-Locking for Receiver Phase Synchronization", 2010 IEEE Radio Frequency Integrated Circuits Symposium, Anaheim, CA, IEEE, pp. 201 - 204, 05/2010. Abstract
Jayaraman, K., Q. A. Khan, B. Chi, W. Beattie, Z. Wang, and P. Y. Chiang, "A Self-Healing 2.4ghz LNA With On-Chip S11/S21 Measurement/Calibration for In-Situ PVT Compensation", 2010 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Anaheim, CA, IEEE, pp. 311 - 314, 05/2010. Abstract
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