Patrick Chiang

Associate Professor
Electrical & Computer Engineering
Education: 
  • University of California - Berkeley,  B.S. Degree, 1998, Electrical Engineering
  • Stanford University, M.S. Degree, 2001, Electrical Engineering
  • Stanford University, Ph.D., 2007, Electrical Engineering
Biography: 

Patrick Chiang received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 2001 and 2007.

In 1998, he was with Datapath Systems (now LSI Logic), working on analog front-ends for DSL chipsets. In 2002 he was a research intern at Velio Communications (now Rambus) working on 10GHz clock synthesis architectures. In 2004 he was a consultant at startup Telegent Systems, evaluating low phase noise VCOs for CMOS mobile TV tuners. In 2006 he was a visiting NSF postdoctoral researcher at Tsinghua University, China, investigating low power, low voltage RF transceivers. In 2009 he was a visiting senior researcher at the ASIC State & Key Laboratory in Fudan University, Shanghai, China.

His interests are: 1) The design of energy-efficient, CMOS interconnects (on-chip/off-chip/wireless) — Energy-efficient interfaces will soon be a dominant portion of the power budget on future microprocessors and SoCs. These include on-chip links, off-chip multi-gigahertz I/O, and wireless data transmission. We are investigating new techniques in advanced CMOS processes to enable improved energy-efficiency (pJ/bit-transferred).

2) Wireless, wearable medical sensors — Advances in semiconductor technology will soon enable “bandaid-size” medical sensors, non-invasively attached to the human body, allowing for non-invasive monitoring of human activity. These sensors will capture measurement of minute electrical signals (i.e. brain-EEG signals, heart-ECG waves, accelerometer-based activity monitoring), which will provide continuous monitoring of medical condition, such as disease onset, vitamin/drug efficacy, sleep diagnosis, and brain cognition.

Research Interests: 

Research Areas
Energy-efficient CMOS interconnects (gigahertz ADCs, wireline on/off chip I/O, wireless); Wireless medical electronics

2010
Crop, J., S. Fairbanks, R. Pawlowski, and P. Y. Chiang, "150mV sub-threshold Asynchronous multiplier for low-power sensor applications", 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsin Chu, Taiwan, IEEE, pp. 254 - 257, 04/2010. Abstract
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Jiang, T., and P. Y. Chiang, "Energy-efficient, decision feedback equalization Using SAR-like capacitive charge summation", 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsin Chu, Taiwan, IEEE, pp. 249 - 252, 04/2010. Abstract
Albright, R. K., B. J. Goska, and P. Y. Chiang, "A Wireless Transceiver Platform for Comparing Various ISM Bands for Next-Generation Body Area Networks", AMA-IEEE Medical Technology Conference on Individualized Healthcare, Washington DC, 03/2010.
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Krimer, E., R. Pawlowski, M. Erez, and P. Y. Chiang, "Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications", IEEE Computer Architecture Letters, vol. 9, issue 1, pp. 21 - 24, 01/2010. Abstract
2009
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Chi, B., J. Yao, P. Y. Chiang, and Z. Wang, "A 0.18-um CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, issue 11, pp. 2498 - 2510, 11/2009. Abstract
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Feng, Z., Y. Yi, Y. Zongren, P. Y. Chiang, and H. Weiwu, "A low latency transceiver macro with robust design technique for processor interface", 2009 IEEE Asian Solid-State Circuits Conference (A-SSCC), Taipei, Taiwan, IEEE, pp. 185 - 188, 11/2009. Abstract
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Gao, Z., H. Yu, P. Y. Chiang, Y. Yang, and F. Zhang, "A 10Gb/s wire-line transceiver with half rate period calibration CDR", IEEE International Symposium on Circuits and Systems - ISCAS 2009, Taipei, Taiwan, IEEE, pp. 1827 - 1830, 05/2009. Abstract
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Hu, K., T. Jiang, and P. Y. Chiang, "Comparison of on-die global clock distribution methods for parallel serial links", IEEE International Symposium on Circuits and Systems - ISCAS 2009, Taipei, Taiwan, IEEE, pp. 1843 - 1846, 05/2009. Abstract
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Jiang, T., and P. Y. Chiang, "Sense amplifier power and delay characterization for operation under low-Vdd and low-voltage clock swing", IEEE International Symposium on Circuits and Systems - ISCAS 2009, Taipei, Taiwan, IEEE, pp. 181 - 184, 05/2009. Abstract
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Jayaraman, K., Q. A. Khan, P. Y. Chiang, and B. Chi, "Design and analysis of 1–60GHz, RF CMOS peak detectors for LNA calibration", International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, IEEE, pp. 311 - 314, 04/2009. Abstract
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Chi, B., J. Yao, P. Y. Chiang, and Z. Wang, "A Fast-Settling Wideband-IF ASK Baseband Circuit for a Wireless Endoscope Capsule", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, issue 4, pp. 275 - 279, 04/2009. Abstract