Patrick Chiang

Associate Professor
Electrical & Computer Engineering
Education: 
  • University of California - Berkeley,  B.S. Degree, 1998, Electrical Engineering
  • Stanford University, M.S. Degree, 2001, Electrical Engineering
  • Stanford University, Ph.D., 2007, Electrical Engineering
Biography: 

Patrick Chiang received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 2001 and 2007.

In 1998, he was with Datapath Systems (now LSI Logic), working on analog front-ends for DSL chipsets. In 2002 he was a research intern at Velio Communications (now Rambus) working on 10GHz clock synthesis architectures. In 2004 he was a consultant at startup Telegent Systems, evaluating low phase noise VCOs for CMOS mobile TV tuners. In 2006 he was a visiting NSF postdoctoral researcher at Tsinghua University, China, investigating low power, low voltage RF transceivers. In 2009 he was a visiting senior researcher at the ASIC State & Key Laboratory in Fudan University, Shanghai, China.

His interests are: 1) The design of energy-efficient, CMOS interconnects (on-chip/off-chip/wireless) — Energy-efficient interfaces will soon be a dominant portion of the power budget on future microprocessors and SoCs. These include on-chip links, off-chip multi-gigahertz I/O, and wireless data transmission. We are investigating new techniques in advanced CMOS processes to enable improved energy-efficiency (pJ/bit-transferred).

2) Wireless, wearable medical sensors — Advances in semiconductor technology will soon enable “bandaid-size” medical sensors, non-invasively attached to the human body, allowing for non-invasive monitoring of human activity. These sensors will capture measurement of minute electrical signals (i.e. brain-EEG signals, heart-ECG waves, accelerometer-based activity monitoring), which will provide continuous monitoring of medical condition, such as disease onset, vitamin/drug efficacy, sleep diagnosis, and brain cognition.

Research Interests: 

Research Areas
Energy-efficient CMOS interconnects (gigahertz ADCs, wireline on/off chip I/O, wireless); Wireless medical electronics

2009
Zhuo, G., D. Kesharwani, P. Y. Chiang, and H. Weiwu, "Measuring and compensating for process mismatch-induced, reference spurs in phase-locked loops using a sub-sampled DSP", IEEE International Symposium on Circuits and Systems - ISCAS 2009, Taipei, Taiwan, IEEE, pp. 1585 - 1588, 04/2009. Abstract
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Hu, C., S. Redfield, H. Liu, R. Khanna, J. Nejedlo, and P. Y. Chiang, "Transmitter equalization for multipath interference cancellation in impulse radio ultra-wideband (IR-UWB) transceivers", 2009 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, IEEE, pp. 307 - 310, 04/2009. Abstract
Hu, C., S. Redfield, H. Liu, R. Khanna, J. Nejedlo, and P. Y. Chiang, "Transmitter equalization for multipath interference cancellation in impulse radio ultra-wideband (IR-UWB) transceivers", International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, IEEE, pp. 307 - 310, 04/2009. Abstract
2008
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Krishna, T., A. Kumar, P. Y. Chiang, M. Erez, and L. - S. Peh, "NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication", IEEE Symposium on High Performance Interconnects, Stanford, CA, IEEE, pp. 11 - 20, 08/2008. Abstract
2007
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Cui, Y., B. Chi, M. Liu, Y. Zhang, Y. Li, Z. Wang, and P. Y. Chiang, "Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance", 2007 IEEE International Symposium on Circuits and Systems, New Orleans, LA, IEEE, pp. 2562 - 2565, 05/2007. Abstract
2005
2004
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2002
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Chiang, P. Y., B. Dally, and M. - J. E. Lee, "A 20Gb/s 0.13um CMOS Serial Link", Hotchips, Stanford, CA, pp. 1-3, 08/2002. Abstract
2001
Lee, M. - J. E., W. J. Dally, J. W. Poulton, P. Y. Chiang, and S. E. Greenwood, "An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications", Symposium on VLSI Circuits, Kyoto, Japan, Japan Soc. Appl. Phys, pp. 149 - 152, 06/2001. Abstract
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Chiang, P. Y., W. Dally, and E. Lee, "Monolithic chaotic communications system", IEEE International Symposium on Circuits and Systems, vol. 2, Sydney, NSW, Australia, IEEE, pp. 325 - 328, 05/2001. Abstract
2000
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Lee, M. - J. E., W. J. Dally, and P. Y. Chiang, "Low-power area-efficient high-speed I/O circuit techniques", IEEE Journal of Solid-State Circuits, vol. 35, issue 11, pp. 1591 - 1599, 11/2000. Abstract
Lee, M. - J. E., W. Dally, and P. Y. Chiang, "A 90 mW 4 Gb/s equalized I/O circuit with input offset cancellation", IEEE International Solid-State Circuits Conference, San Francisco, CA, IEEE, pp. 252 - 253, 02/2000. Abstract
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1999
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Conroy, C., S. Sheng, A. Feldman, G. Uehara, A. Yeung, C. - J. Hung, V. Subramanian, P. Y. Chiang, P. Lai, X. Si, et al., "A CMOS analog front-end IC for DMT ADSL", IEEE International Solid-State Circuits Conference, San Francisco, CA, IEEE, pp. 240 - 241, 02/1999. Abstract