Pavan Kumar Hanumolu

Assistant Professor

Electrical & Computer Engineering

Web Page:

http://web.engr.oregonstate.edu/~hanumolu/

Biography:

Pavan Kumar Hanumolu received the B.E. (Hons.) degree in electrical and electronics engineering and the M.Sc. (Hons.) degree in mathematics from the Birla Institute of Technology and Science, Pilani, India, in 1998, the M.S. degree in electrical and computer engineering from the Worcester Polytechnic Institute, Worcester, MA, in 2001, and the Ph.D. degree in electrical engineering at Oregon State University, Corvallis, in 2006.

From 1998 to 1999, he was a Design Engineer at Cypress Semiconductors, Bangalore, India, working on phase-locked loops for LVDS interfaces. During the summers of 2002 and 2003, he was with Intel Circuits Research Labs, Hillsboro, OR, where he investigated clocking and equalization schemes for input/output (I/O) interfaces. He is currently an Assistant Professor in the School of EECS at Oregon State University, Corvallis.

His current research interests include equalization, clocking circuits for high-speed I/O interfaces, data converters, digital techniques to compensate for analog circuit imperfections, power management circuits, and built-in self-test (BIST) of analog circuits.

Research group:

Analog/Mixed-Signal - RF - Microwaves

Research Interests:

Our research focuses on five main aspects of analog, mixed-signal circuits and systems:

Low-power system architectures and circuits for intra-chip communication
Scalable, high performance phase-locked loops
Built-in self-test (BIST) of analog and mixed-signal circuits
Low-power, low-voltage data converter techniques
Power management circuits for mobile applications

Teaching:

ECE 520 ANALOG CMOS INTEGRAT CIRCUITS

Publications

In Press

Tong, T., P. K. Hanumolu, and G. C. Temes, "A Semi-synchronuous SAR ADC", Analog Integrated Circuits and Signal Processing, In Press.

2011

Wang, Y., P. K. Hanumolu, and G. C. Temes, "Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, issue 7, pp. 1518 - 1530, 07/2011. Abstract

Vytyaz, I., P. K. Hanumolu, U. Moon, and K. Mayaram, "Design-Oriented Analysis of Circuits With Equality Constraints", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, issue 5, pp. 1089 - 1098, 05/2011. Abstract

2010

Gubbins, D., B. Lee, P. K. Hanumolu, and U. Moon, "Continuous-Time Input Pipeline ADCs", IEEE Journal of Solid-State Circuits, vol. 45, issue 8, pp. 1456 - 1468, 08/2010. Abstract

2009

Weaver, S. T., B. P. Hershberg, P. K. Hanumolu, and U. Moon, "A multiplexer-based digital passive linear counter (PLINCO)", 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009), Yasmine Hammamet, Tunisia, IEEE, pp. 607 - 610, 12/2009. Abstract

Agrawal, A., A. Liu, P. K. Hanumolu, and G. - Y. Wei, "An 8x5 Gb/s Parallel Receiver With Collaborative Timing Recovery", IEEE Journal of Solid-State Circuits, vol. 44, issue 11, pp. 3120 - 3130, 11/2009. Abstract

Kim, M. G., P. K. Hanumolu, and U. Moon, "A 10 MS/s 11-bit 0.19mm2 Algorithmic ADC With Improved Clocking Scheme", IEEE Journal of Solid-State Circuits, vol. 44, issue 9, pp. 2348 - 2355, 09/2009. Abstract

Kwon, S., P. K. Hanumolu, S. - H. Kim, S. - N. Lee, S. - B. You, H. - J. Park, J. - W. Kim, and U. Moon, "An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing", 2009 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 171 - 174, 09/2009. Abstract

Gubbins, D., S. Kwon, B. Lee, P. K. Hanumolu, and U. Moon, "A continuous-time input pipeline ADC with inherent anti-alias filtering", 2009 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 275 - 278, 09/2009. Abstract

Sasidhar, N., Y. - J. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. K. Hanumolu, and U. Moon, "A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback", IEEE Journal of Solid-State Circuits, vol. 44, issue 9, pp. 2392 - 2401, 09/2009. Abstract

Kratyuk, V., P. K. Hanumolu, K. Ok, U. Moon, and K. Mayaram, "A Digital PLL With a Stochastic Time-to-Digital Converter", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, issue 8, pp. 1612 - 1621, 08/2009. Abstract

Arakali, A., S. Gondi, and P. K. Hanumolu, "Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture", IEEE Journal of Solid-State Circuits, vol. 44, issue 8, pp. 2169 - 2181, 08/2009. Abstract

Rajaee, O., T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P. K. Hanumolu, and U. Moon, "A 79dB 80 MHz 8X-OSR hybrid delta-sigma/pipeline ADC", IEEE Symp. VLSI Circuits, Kyoto, Japan, pp. 74 -75, 06/2009. Abstract

Vytyaz, I., D. C. Lee, P. K. Hanumolu, U. Moon, and K. Mayaram, "Automated Design and Optimization of Low-Noise Oscillators", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, issue 5, pp. 609 - 622, 05/2009. Abstract

Wu, T., P. K. Hanumolu, K. Mayaram, and U. Moon, "Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers", IEEE Journal of Solid-State Circuits, vol. 44, issue 2, pp. 427 - 435, 02/2009. Abstract

2008

Kim, M. G., V. Kratyuk, P. K. Hanumolu, G. - C. Ahn, S. Kwon, and U. Moon, "An 8mW 10b 50MS/s pipelined ADC using 25dB opamp", 2008 IEEE Asian Solid-State Circuits Conference (A-SSCC), Fukuoka, Japan, IEEE, pp. 49 - 52, 11/2008. Abstract

Arakali, A., S. Gondi, and P. K. Hanumolu, "A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of −28dB", 2008 IEEE Custom Integrated Circuits Conference - CICC 2008, San Jose, CA, IEEE, pp. 443 - 446, 09/2008. Abstract

Kurahashi, P., P. K. Hanumolu, and U. Moon, "A 1V downconversion filter using duty-cycle controlled bandwidth tuning", 2008 IEEE Custom Integrated Circuits Conference - CICC 2008, San Jose, CA, IEEE, pp. 707 - 710, 09/2008. Abstract

Agrawal, A., P. K. Hanumolu, and G. - Y. Wei, "A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction", 2008 IEEE Custom Integrated Circuits Conference - CICC 2008, San Jose, CA, IEEE, pp. 459 - 462, 09/2008. Abstract

Gubbins, D., B. Lee, P. K. Hanumolu, and U. Moon, "A continuous-time input pipeline ADC", 2008 IEEE Custom Integrated Circuits Conference - CICC 2008, San Jose, CA, IEEE, pp. 169 - 172, 09/2008. Abstract

Vytyaz, I., J. Carnes, T. Wu, P. K. Hanumolu, U. Moon, and K. Mayaram, "Noise tolerant oscillator design using perturbation projection vector analysis", 2008 IEEE Custom Integrated Circuits Conference - CICC 2008, San Jose, CA, IEEE, pp. 695 - 698, 09/2008. Abstract

Vytyaz, I., D. C. Lee, P. K. Hanumolu, U. Moon, and K. Mayaram, "Sensitivity Analysis for Oscillators", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, issue 9, pp. 1521 - 1534, 09/2008. Abstract

Arakali, A., N. Talebbeydokthi, S. Gondi, and P. K. Hanumolu, "Supply-noise mitigation techniques in phase-locked loops", ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, UK, IEEE, pp. 374 - 377, 09/2008. Abstract

Kim, M. G., G. - C. Ahn, P. K. Hanumolu, S. - H. Lee, S. - H. Kim, S. - B. You, J. - W. Kim, G. C. Temes, and U. Moon, "A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC", IEEE Journal of Solid-State Circuits, vol. 43, issue 5, pp. 1195 - 1206, 05/2008. Abstract

Vytyaz, I., P. K. Hanumolu, U. Moon, and K. Mayaram, "Periodic Steady-State Analysis Augmented with Design Equality Constraints", 2008 Design, Automation and Test in Europe, Munich, Germany, IEEE, pp. 312 - 317, 03/2008. Abstract

School of Electrical Engineering & Computer Science