July 2017

ELECTRICAL & COMPUTER ENGINEERING

OREGON STATE UNIVERSITY

College of Engineering

## TEMES, Gabor C.

Professor

### DEGREES

- Dipl. Ing. (B.S.), Electrical Engineering, Technical University of Budapest, 1952
- Dipl. Phys. (B.S.), Physics, Eotvos University, 1955
- Ph.D., Electrical Engineering, University of Ottawa, 1961
- D.Eng. (honorary), Technical University of Budapest, 1991

### ACADEMIC POSITIONS

- Lecturer, Technical University of Budapest, October 1951-October 1952
- Assistant Professor, Technical University of Budapest, October 1952-November 1956
- Lecturer, Sherbrooke University, Canada, January 1957-May 1957
- Lecturer, University of Ottawa, October 1961-April 1964
- Lecturer, University of Santa Clara, May 1966-September 1969
- Lecturer, Stanford University, September 1966-June 1966
- Professor, Department of Electrical Engineering, University of California, 1970-1990; Department Chair, 1975-1979
- Visiting Professor, Technical University of Munich, July 1979-August 1979
- Professeur Invite, Ecole Polytechnique Federale de Lausanne, April 1985-August 1985
- Professor, Department of Electrical and Computer Engineering, Oregon State University, 1990-present; Department Head, 1990-1994

### NON-ACADEMIC POSITIONS

- Project Engineer, Measurement Engineering Ltd., June 1957-April 1959
- Laboratory Supervisor, Northern Electric R & D Labs, April 1959-April 1964
- Research Group Leader, Stanford University, April 1964-April 1966
- Corporate Consultant, Ampex Corporation, April 1966-August 1969

Consultant to:

- Xerox Corp. Microelectronics, Redondo Beach, CA, 1980-1987
- AEG Telefunken Backnang, West Germany, 1980-1987
- Hughes Research Labs, Malibu, CA, 1987-1990, 2008-present
- Tektronix, Beaverton, OR, 1991-1992
- Microchip, Switzerland, 2002-2004
- Cypress Semiconductor, 2006-2009
- EGI Inc., 2006-2009

### FIELDS OF SPECIALIZATION

- Data Converters
- Switched-Capacitor Circuits
- Analog and Digital Signal Processing

### PROFESSIONAL ACTIVITIES

#### Professional Societies

Institute of Electrical and Electronics Engineers (IEEE)

- IEEE Circuits and Systems Society (CAS)

#### Professional Recognition

- Darlington Award of the IEEE CAS Society (with H.J. Orchard), 1969
- Fellow of IEEE, 1972
- Darlington Award of the IEEE CAS Society (with M.S. Lee, C. Chang, and M. Ghaderi), 1981
- Outstanding Engineer Merit Award of IAE, 1981
- Western Electric Fund Award of ASEE, 1982
- IEEE Centennial Medal, 1984
- Andrew Chi Prize of IEEE I&M Society, 1985
- Education Award, IEEE CAS Society, 1987
- Distinguished Professor, 1988-1990; Distinguished Emeritus Professor, 1990- , UCLA
- Technical Achievement Award, IEEE CAS Society, 1989
- Honorary Doctorate, Technical University of Budapest, 1991
- Senior Research Award, Humboldt Foundation, Germany, 1991
- Distinguished Lecturer, IEEE-CAS, 1991-1992
- Best Evening Panel Award, 1996 International Solid-State Circuits Conference, February 1996
- IEEE Graduate Teaching Award, 1998
- Member, Review Team to evaluate the ECE Department at the University of Toronto, May 1999
- Keynote Speaker, 42nd IEEE Midwest Symposium on Circuits and Systems, August 1999
- IEEE Circuits and Systems Society Golden Jubilee Medal, 1999
- IEEE Third Millenium Medal, 2000
- CDADIC Best Project Award, February 2001
- Plenary Speaker, VII Iberchip Workshop, Montevideo, Uruguay, March 2001
- IEEE CAS Society Distinguished Lecturer, 2001/2
- Distinguished Lecturer, University of Toronto, 2004
- Invited Speaker, U.C. Berkeley IC Seminar Oct. 4, 2005
- Distinguished Lecturer, UCLA, Jan. 23, 2006
- IEEE Gustav Robert Kirchhoff Award, Feb. 2006
- IEEE CAS Mac Van Valkenburg Award, May 2009
- OSU COE Research Award, Sept. 2010
- “Gabor Temes: Creativity in Analog Circuits,” Special Issue of the IEEE Solid-State Circuits Magazine, vol. 5, No. 2, Spring 2013.
- National Academy of Engineering, Febr. 2015
- 2017 SIA-SRC University Researcher Award

#### Committees, Commissions and Boards

**Institute of Electrical and Electronics Engineers**

Circuits and Systems Society

- Chair, Technical Program Committee, Symposium on Circuits and Systems, 1970
- Administrative Committee, 1973-1974
- Best Paper Award Committee Chairman, 1974-1975
- Fellow Award Committee, 1974-1980
- Nominations Committee Chairman, 1978-1979
- Awards Committee, 1985-1988, 1998-1999
- Service Award Committee Chairman, 1986-1987
- Teaching Award Committee Chairman, 1987-1993
- Vice President, 1967-1969, 1971-1972
- Valkenburg Award Committee Chairman, 1998-1999, 2009-2010
- Fellow Award Committee, 2001
- Technical Achievement Award Committee, 2002-2003, 2009-2010
- Teaching Award Committee, 2005-2008
- Gustav Robert Kirchhoff Award Committee, 2006-2008
- Vitold Belevitch Award Committee Chairman 2013
- Vitold Belevitch Award Committee, 2008-2009
- Charles Desoer Research Award Committee, 2014-2015
- CAS John Choma Education Award Committee, 2016-2017

Education Group

- Fellow Award Committee, 1976-1978

IEEE Transactions on Circuit Theory

- Guest Editor, Special Issue on Modern Filter Design, 1968
- Associate Editor, 1967-1969
- Editor, 1969-1971

Journal of the Franklin Institute

- Member of the Board of Associate Editors, 1971-1973

IEEE Trans. on Circuits and Systems and IEEE Trans. on Communications

Proceedings of the IEEE

- Guest Editor, 1983
- Member of Editorial Board, 1989-1994

Circuits, Systems and Signal Processing

- Associate Editor, 1984-1989

Analog Integrated Circuits and Signal Processing, Kluwer

- Associate Editor, 1992-present

Advisory Committee, Ph.D. Program, Polytechnic, Institute of Turin, Italy, 1981-1982

Scientific Advisory Board, Information Technology Research Centre (University of Toronto), 1989-1991

International Expert Commission, National Center for Microelectronics, Spain, 1990-1991

### PUBLICATIONS

#### Books, Chapters in Books, and Editorships

- Temes, G.C.,
*Electronphysics*, Technical University Press, Budapest, 1953.
- Berkes, T. and Temes, G.C.,
*Nuclear Physics Measurements*, Technical University Press, Budapest, 1956.
- Temes, G.C. and Kalman, G.,
*Selected Problems in Electronphysics*, Technical University Press, Budapest, 1956.
- Temes, G.C., “Interaction Between the Energy-Losses of Protons in Free Electron Gas,” KFKI Kozlemenyek,
*Proc. of the Central Research Inst. of Physics*, Budapest, 1957, 5:77-83.
- Temes, G.C., Boire, P., and Banfill, H., “A New Brightness Meter,”
*Proc. of the Instrument Soc. of America*, June 1960, pp. 6-1 to 6-8.
- Temes, G.C., “Optimization Methods in Circuit Design,” and “Filter Design in Transformed Frequency Variable,” Chapters 5 and 6 in
*Computer Oriented Circuit Design*, F.F. Kuo and W.C. Magnuson, eds., Prentice-Hall, pp. 191-303, October 1969.
- Smith, B.R. and Temes, G.C., “An Iterative Approximation Procedure for Automatic Filter Synthesis,” in
*Computer-Aided Filter Design*, G. Szentirmai , ed., IEEE Press, New York, pp. 11-16, 1973.
- Temes, G.C. and Gyi, M., “Design of Filters with Arbitrary Passband and Chebyshev Stopband Attenuation,” in
*Computer-Aided Filter Design*, G. Szentirmai, ed., IEEE Press, New York, pp. 20-21, 1973.
- Orchard, H.J. and Temes, G.C., “Filter Design Using Transformed Variables,” in Computer-Aided Filter Design, G. Szentirmai, ed., IEEE Press, New York, pp. 90-113, 1973.
- Temes, G.C. and Calahan, D.A., “Computer-Aided Network Optimization--The State of the Art,” in
*Computer-Aided Filter Design*, G. Szentirmai, ed., IEEE Press, New York, pp. 187-218, 1973.
- Temes, G.C. and Zai, DY.F., “Least pth Approximation,” in
*Computer-Aided Filter Design*, G. Szentirmai, ed., IEEE Press, New York, pp. 219-221, 1973.
- MacDonald, J.D. and Temes, G.C., “A Simple Method for the Predistortion of Filter Transfer Functions,” in
*Computer-Aided Filter Design*, G. Szentirmai, ed., IEEE Press, New York, pp. 248-251, 1973.
- Smith, B.R. and Temes, G.C., “An Iterative Approximation Procedure for Automatic Filter Synthesis,” in
*Computer-Aided Circuit Design Simulation and Optimization*, S.W. Director, ed., Dowden, Hutchingson & Ross, Inc., Stroudsburg, PA, pp. 226-231, 1973.
- Temes, G.C. and Mitra, S.K., eds.,
*Modern Filter Theory and Design*, Wiley, New York, November 1973.
- Temes, G.C. and Mitra, S.K., eds.,
*Modern Filter Theory and Design*, Russian Translation, MIR Publishing Co., Moscow, 1977; also translated into Polish.
- Temes, G.C. and La Patra, J.W.,
*Introduction to Circuit Synthesis and Design*, McGraw-Hill, New York, 1977; Far East Edition, 1980.
- Temes, G.C., Orchard, H.J., and Jahanbegloo, M., “Switched-Capacitor Filter Design Using the Bilinear z-Transform,” in
*Analog MOS Integrated Circuits*, P.R. Gray, D.A. Hodges, and R.W. Brodersen, eds., IEEE Press, New York, pp. 275-280, 1980.
- Temes, G.C., Orchard, H.J., and Jahanbegloo, M., “Switched-Capacitor Filter Design Using the Bilinear z-Transform,” in
*Modern Active Filter Design*, R. Schaumann, M.A. Soderstrand, and K.R. Laker, eds., IEEE Press, New York, pp. 318-323, 1981.
- Gregorian, R., Martin, K.W., and Temes, G.C., “Switched-Capacitor Circuit Design,” in
*MOS Switched-Capacitor Filters*, G. Moschytz, ed., IEEE Press, New York, pp. 180-205, 1984.
- Lee, M.S., Temes, G.C., Chang, C., and Ghaderi, B., “Bilinear Switched-Capacitor Ladder Filter,” in
*MOS Switched-Capacitor Filters*, G. Moschytz, ed., IEEE Press, New York, pp. 325-335, 1984.
- Temes, G.C., Orchard, H., and Jahanbegloo, M., “Switched-Capacitor Filter Design Using the Bilinear z-Transform,” in
*MOS Switched-Capacitor Filters*, G. Moschytz, ed., IEEE Press, New York, pp. 319-324, 1984.
- Gregorian, R. and Temes, G.C.,
*Analog MOS Integrated Circuits for Signal Processing*, Wiley, New York, 1986.
- Temes, G.C., ed.,
*Integrated Analog Filters*, IEEE Press, New York, 1988.
- Gregorian, R. and Temes, G.C., “Switched-Capacitor Filters: Circuits and Applications,” Chapter 5 in
*Miniaturized and Integrated Filters*, Wiley, New York, NY, pp. 159-219, 1989.
- Candy, J.C. and Temes, G.C., eds.,
*Oversampling Delta-Sigma Data Converters*, IEEE Press, New York, NY, 1991. Also co-author of the introductory paper of the book.
- Larson, L.E. and Temes, G.C., “Signal Conditioning and Interface Circuits,” Chapter 10 in
*Digital Signal Processing Handbook*, Wiley, New York, NY, pp. 677-720, 1993.
- Temes, G.C., “Delta-Sigma Data Converters,” Chapter 10 in
*Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing*, J. Franca and Y. Tsividis, eds., Prentice-Hall, Englewood Cliffs, NJ, pp. 317-340, 1994.
- Temes, G.C., “Delta-Sigma D/A Converters,” Chapter 4.2 in
*Circuits and Systems Tutorials*, Ch. Toumazou, ed., IEEE, 1994, pp. 224-234.
- Norsworthy, S., Schreier, R., and Temes, G.C., eds.,
*Delta-Sigma Data Converters*, IEEE Press, New York, NY, 1996. Also, coauthor of Chapters 8 and 10.
- Temes, G., “Autozeroing and Correlated Doubling Sampling,” in
*Analog Circuit Design*, J. Huising, R. van de Plassche, and W. Sansen, eds., Kluwer, Dordrecht, Netherlands, pp. 45-64, 1996.
- Schreier, R., Steensgaard, J., and Temes, G., “Speed vs. Dynamic Range Trade-Off in Oversampling Data Converters,” Chapter 21 in:
*Trade-Offs in Analog Integrated Circuits*, B. Gilbert, G. Moschytz, and Ch. Toumazou, eds., Wiley, 2002.
- Schreier, R. and Temes, G.C.,
*Understanding Delta-Sigma Data Converters*, IEEE Press/Wiley Interscience, 2005. Japanese translation, 2007, published by Maruzen Co.; Chinese ed. by Sciencep, 2007 (?).
- Lee, K. and Temes, G.C., “Noise-Coupled Delta-Sigma ADCs, in
*Analog Circuit Design*, Springer, 2011.
- Temes, G.C., “Incremental and Extended-Range Data Converters,” in
*Design, Modeling and Testing of Data Converters, *Springer, 2013.
- Chen, C-H, He, T. and Temes, G.C. “Micro-power incremental ADCs,” in
*Analog Circuit Design*, Springer, 2015.
- Temes, G.C. “Delta-Sigma Data Converters,” in
*A Brief History of Circuits and Systems*, IEEE, 2016.
- Pavan, S., Schreier, R. and Temes, G.C.,
*Understanding Delta-Sigma Data Converters*, second edition, IEEE Press/Wiley Interscience, 2017.

#### Technical Journals

- Temes, G.C., “Integrator-Type Frequency Dividers and Counters,”
*Hiradastechnika*, Budapest, 1954.
- Fodor, G. and Temes, G.C., “Analog Computing Circuits,”
*Meres es Automatika*, Budapest, 1955.
- Fodor, G. and Temes, G.C., “Differentiating Networks,”
*Hiradastechnika*, Budapest, 1955.
- Fodor, G. and Temes, G.C., “Differentiating and Integrating Networks,”
*Acta Technica Hungarica*, 16:73-104, Budapest, 1957 (in English).
- Temes, G.C., “Interaction Between the Energy-Losses of Protons in Free Electron Gas,” KFKI Kozlemenyek,
*Proc. of the Central Research Inst. of Physics*, Budapest, 1957, 5:77-83.
- Temes, G.C., Boire, P., and Banfill, H., “A New Brightness Meter,”
*Proc. of the Instrument Soc. of America*, June 1960, pp. 6-1 to 6-8.
- Temes, G.C., “The Synthesis of General Parameter Filters,”
*Communications & Electronics*, 80-54:181-186, May 1961.
- Schwelb, O. and Temes, G.C., “The Design of Thermistor-Resistor Temperature Sensing Devices,”
*Electro-Technology*, 68(5):71-75, November 1961.
- Temes, G.C., “An Additional Extension of a Network Theorem,”
*Inst. of Radio Engineers Trans. on Circuit Theory*, 8:488-489, December 1961.
- Temes, G.C., “Optimal Selectivity of Harmonic Suppressing Filter Sets,”
*Inst. of Radio Engineers Trans. on Circuit Theory*, 9(2):187-188, June 1962.
- Temes, G.C., “First-Order Estimation and Precorrection of Parasitic Effects in Filters,”
*Inst. of Radio Engineers Trans. on Circuit Theory*, 9:385-399, December 1962.
- Temes, G.C. and Saal, R., “Comments on the Design of Filters by Synthesis,”
*Inst. of Radio Engineers Trans. on Circuit Theory*, 9:409-410, December 1962.
- Mac Donald, J.D. and Temes, G.C., “A Simple Method for the Predistortion of Filter Transfer Functions,”
*Inst. of Radio Engineers Trans. on Circuit Theory*, 10:447-450, September 1963.
- Temes, G.C., “The Synthesis of Filters with Maximally Flat Passband and Arbitrary Stopband Attenuation,”
*Canadian Electronics Engineering*, 8:29-33, February 1964.
- Smith, B.R. and Temes, G.C., “An Iterative Approximation Procedure for Automatic Filter Synthesis,”
*IEEE Trans. on Circuit Theory*, 12:107-112, March 1965.
- Christian, E. and Temes, G.C., “On the Szentirmai Transformation,”
*IEEE Trans. on Circuit Theory*, 13:450-452, December 1966.
- Temes, G.C. and Bingham, J.A.C., “Iterative Chebyshev Approximation for Network Synthesis,”
*IEEE Trans. on Circuit Theory*, 14:31-37, March 1967.
- Szego, P., Temes, G.C., and Orchard, H.J., “Optimum Band-Limited System with Monotonic Step Response,”
*Proc. of the IEEE*, 55:698-700, May 1967.
- Temes, G.C. and Calahan, D.A., “Computer-Aided Network Optimization - the State of the Art,”
*Proc. of the IEEE*, 55:1832-1863, November 1967.
- Temes, G.C. and Orchard, H.J., “Maximally Flat Approximation Techniques,”
*Proc. of IEEE*, 56:65-66, January 1968.
- Orchard, H.J. and Temes, G.C., “Filter Design Using Transformed Variables,”
*IEEE Trans. on Circuit Theory*, 15:486-508, New York, December 1968.
- Temes, G.C., “The Present and Future of Filter Theory,”
*IEEE Trans. on Circuit Theory*, 15:302, December 1968.
- Temes, G.C., “Computer-Aided Electrical Circuit Design,”
*Readout*, 8(2):14-15, February 1969.
- Temes, G.C. and Zai, D., “Least pth Approximation,”
*IEEE Trans. on Circuit Theory*, 16:235-237, May 1969.
- Temes, G.C., “A Physical Proof of Tellegen’s Theorem,”
*Proc. of the IEEE*, 57(6):1183-1184, June 1969.
- Temes, G.C., “Exact Computation of the Group Delay and its Sensitivities Using the Adjoint Network Concept,”
*Electronic Letters*, 6(15):483-485, July 23, 1970.
- Temes, G.C., “Circuit Theory of the 1970's,”
*IEEE Trans. on Circuit Theory*, 17:468, November 1970.
- Temes, G.C. and Gadenz, R.N., “Simple Technique for the Prediction of Dissipation-Induced Loss Distortion,”
*Electronic Letters*, 6:836-837, December 1970.
- Gadenz, R.N. and Temes, G.C., “Computation of Dissipation-Induced Loss Distortion in Lumped-Distributed Networks,”
*Electronic Letters*, 7:10, May 1971.
- Gadenz, R.N. and Temes, G.C., “An Efficient Procedure for the Statistical Transient Analysis of Switching Circuits,”
*Computer-Aided Design*, 3(4):19-25, Summer 1971.
- Hayes, L.L. and Temes, G.C., “An Efficient Numerical Method for the Computation of Zero-and Pole-Sensitivities,”
*Int. J. of Electronics*, 1(11):21-31, 1972.
- Temes, G.C., “The Prolate Filter: An Ideal Lowpass Filter with Optimum Step-Response,”
*J. of the Franklin Inst.*, 293:77-103, February 1972.
- Temes, G.C., “Effects of Semiuniform Losses in Reactance Two-Ports,”
*Electronic Letters*, 8:161-163, March 1972.
- Temes, G.C., Ebers, R.M., and Gadenz, R.N., “Some Novel Applications of the Adjoint Network Concept in Frequency-Domain Circuit Analysis and Optimization,”
*Computer-Aided Design*, 4:129-134, April 1972.
- Temes, G.C. and Barcilon, F., “A Lower Bound for the Minimum Risetime of Bandlimited Systems,”
*IEEE Trans. on Circuit Theory*, CT-19:280-282, May 1972.
- Temes, G.C., Kurtz, J., and Orchard, H.J., “Least Squares Passband Filters,”
*IEEE Trans. on Circuit Theory*, CT-19:302-304, May 1972.
- Gadenz, R.N. and Temes, G.C., “A Computational Algorithm for the Design of Elliptic Filters,”
*Electronics Letters*, 8:323-324, June 29, 1972.
- Barcilon, V. and Temes, G.C., “Optimum Impulse Response and the van der Maas Function,”
*IEEE Trans. on Circuit Theory*, CT-19:336-342, July 1972.
- Temes, G.C., “Design Formulas for Cascaded Two-Ports,”
*IEEE Trans. on Circuit Theory*, CT-19:528-530, September 1972.
- Gadenz, R.N. and Temes, G.C., “Efficient Hybrid and State-Space Analysis of the Adjoint Network,”
*IEEE Trans. on Circuit Theory*, CT-19:520-521, September 1972.
- Temes, G.C., Barcilon, V., and Marshall, F., “The Optimization of Bandlimited Systems,”
*Proc. of the IEEE*, 61:196-234, February 1973 (invited).
- Marshall, F.C. and Temes, G.C., “Generalized Linear Minimax Approximation of System Functions with Constraints,”
*IEEE Trans. on Circuit Theory*, CT-20:429-432, July 1973.
- Temes, G.C. and Orchard, H.J., “First-Order Sensitivity and Worst-Case Analysis of Doubly Terminated Reactance Twoports,”
*IEEE Trans. on Circuit Theory*, CT-20:567-571, September 1973.
- Gadenz, R.N. and Temes, G.C., “Iterative Compensation Techniques for Lossy or Mismatched Twoports,”
*IEEE Trans. on Circuit Theory*, CT-20:599-603, September 1973.
- Breen, R.H. Jr. and Temes, G.C., “Applications of Golub's Algorithm in Circuit Optimization and Analysis,”
*IEEE Trans. on Circuit Theory*, Special Issue on Computer-Aided Design, CT-20:687-690, November 1973.
- Gadenz, R.N., Rezai-Fakhr, G., and Temes, G.C., “A Method for the Fast Computation of Large Tolerance Effects,”
*IEEE Trans. on Circuit Theory*, Special Issue on Computer-Aided Design, CT-20:704-708, November 1973.
- Orchard, H.J. and Temes, G.C., “A Design Technique for Vestigial Sideband Filters,”
*IEEE Trans. Circuits & Systems*, CAS-21:532-540, July 1974.
- Willson, A.N. Jr., Temes, G.C., and Gadenz, R.N., “On the Active Realization of Lossless Two-Ports,”
*IEEE Trans. on Circuit Theory*, pp. 63-65, January 1975.
- Rezai-Fakhr, M.G. and Temes, G.C., “Statistical Large-Tolerance Analysis on Nonlinear Circuits in the Time Domain,”
*IEEE Trans. on Circuit Theory*, pp. 15-21, January 1975.
- Rezai-Fakhr, M.G. and Temes, G.C., “Node Elimination in Linear Active Circuits,”
*Electronic Letters*, 11:121-122, March 20, 1975.
- Marshall, F.C. and Temes, G.C., “Binary Windows for the Discrete Fourier Transform,”
*Proc. of the IEEE*, pp. 1370-1371, September 1975.
- Temes, G.C., “Multiple Fault Simulation in Linear Active Circuits,”
*Electronics Letters*, 12:467-468, September 2, 1976.
- Babic, H. and Temes, G.C., “Optimum Low-Order Windows for Discrete Fourier Transform Systems,”
*IEEE Trans. on Acoustics, Speech & Signal Processing*, ASSP-24:512-517, December 1976.
- Temes, G.C., “Worst-Case Error Analysis for the Fast Fourier Transform,”
*Electronic Circuits and Systems*, 1(3):110-116, April 1977.
- Temes, G.C., “The Past and Present of Circuit Theory and the CAS Transactions,”
*IEEE Trans. on Circuits and Systems*, CAS-24:671-672, December 1977.
- Temes, G.C. and Cho, K.M., “Large-Change Sensitivity of Linear Digital Networks,”
*IEEE Trans. on Circuits and Systems*, CAS-25(2):113-114, February 1978.
- Temes, G.C., “Graduate Education for Electrical Engineers at UCLA,”
*Creative Science & Technology*, pp. 22-24, February-March 1978.
- Temes, G.C. and Young, I.A., “An Improved Switched-Capacitor Integrator,”
*Electronics Letters*, 14(9):287-288, April 1978.
- Temes, G.C., “The Derivation of Switched-Capacitor Filters from Active-RC Prototype,”
*Electronics Letters*, 14(12):361-362, June 1978.
- Gregorian, R. and Temes, G.C., “Design Techniques for Digital and Analog All-Pass Circuits,”
*IEEE Trans. on Circuits & Systems*, CAS-25(12), 981-988, December 1978.
- Temes, G.C., Orchard, H.J., and Jahanbegloo, M., “Switched-Capacitor Filter Design Using the Bilinear z-Transform,”
*IEEE Trans. on Circuits and Systems*, CAS-25(12):1039-1044, December 1978.
- Temes, G.C. and Jahanbegloo, M., “Switched-Capacitor Circuits Which Are Bilinearly Equivalent to a Floating Inductor or FDNR,”
*Electronics Letters*, 5(3):87-88, February 1, 1979.
- Temes, G.C., Invited Comments, Special Issue on Curriculum Development,
*IEEE Trans. on Education*, p. 42, May 1979.
- Gregorian, R. and Temes, G.C., “Self-Equalizing Sample-and-Hold Circuits,”
*Electronics Letters*, 15(13):367-368, June 1979.
- Temes, G.C. and Gregorian, R., “Compensation for Parasitic Capacitances in Switched-Capacitor Filters,”
*Electronics Letters*, 15(13):377-379, June 1979.
- Nossek, J.A. and Temes, G.C., “Entwurf von Schalter-Kondensator-Filtern mit Hilfe der Bilinearen Transformation,” ("Switched-Capacitor Filter Design with the Aid of the Bilinear Transformation"),
*Archiv fur Elektornik und Ubertragungstechnik*, 34(3):118-124, March 1980.
- Orchard, H.J. and Temes, G.C., “Spectral Analysis of Switched-Capacitor Filters Designed Using the Bilinear z-Transform,”
*IEEE Trans. on Circuits and Systems*, CAS-27:185-190, March 1980.
- Temes, G.C. and Ghaderi, M.B., “Bilinear Switched-Capacitor Ladder Filter with Reduced Number of Amplifiers,”
*Electronics Letters*, 16:412-414, May 22, 1980.
- Temes, G.C., “Finite Amplifiers Gain and Bandwidth Effects in Switched-Capacitor Filters,”
*IEEE J. of Solid-State Circuits*, SC-15:358-361, June 1980.
- Nossek, J. and Temes, G.C., “Switched-Capacitor Filter Design Using Bilinear Element Modeling,”
*IEEE Trans. on Circuits and Systems*, Special Issue on Integrated Filters for Telecommunication, CAS-27:481-491, June 1980.
- Szentirmai, G. and Temes, G.C., “Switched-Capacitor Building Blocks,”
*IEEE Trans. on Circuits and Systems*, Special Issue on Integrated Filters for Telecommunication, CAS-27:492-501, June 1980.
- Muller, G. and Temes, G.C., “A Simple Method for Analysis of a Class of Switched-Capacitor Filters,”
*Electronics Letters*, 16(2):852-853, October 23, 1980.
- Gregorian, R., Nicholson, E., and Temes, G.C., “Integrated Bandsplit Filter System for a Dual-Tone-Multifrequency Receiver,”
*Microelectronics Journal*, 11(6):5-12, November/December 1980.
- Lee, M.S. Temes, G.C., Chang, C., and Ghaderi, M.B., “Bilinear Switched-Capacitor Ladder Filters,”
*IEEE Trans. on Circuits and Systems*, CAS-28:811-822, August 1981.
- Ghaderi, M.B., Temes, G.C., and Law, S., “Linear Interpolation Using CCD’s or Switched-Capacitor Filters,”
*IEEE Proc., Part G, Electronic Circuits and Systems*, pp. 213-215, August 1981 (invited paper).
- Muller, G. and Temes, G.C., “A Pauper’s Algorithm for Switched-Capacitor Circuit Analysis,”
*Electronics Letters*, 17:942-944, December 1981.
- Ghaderi, M.B., Nossek, J.A., and Temes, G.C., “Narrow-Band Switched-Capacitor Bandpass Filters,”
*IEEE Trans. on Circuits and Systems*, CAS-29:557-571, August 1982.
- Shyu, J.B., Temes, G.C., and Yao, K., “Random Errors in MOS Capacitors,”
*IEEE Journal of Solid-State Circuits*, SC-17:1070-1076, December 1982.
- Watanabe, K. and Temes, G.C., “A Switched-Capacitor Digital Multiplier,”
*Electronic Letters*, 19:33-34, January 1983.
- Hsu, T.H. and Temes, G.C., “Improved Input Stage for Bilinear Switched-Capacitor Ladder Filters,”
*IEEE Trans. on Circuits and Systems*, CAS-30:758-760, October 1983.
- Orchard, H.J. and Temes, G.C., “General Sensitivity Formulas for Lossless Two-Ports,”
*Electronics Letters*, 19:576-578, July 1983.
- Gregorian, R., Martin, K.W., and Temes, G.C., “Switched-Capacitor Circuit Design,”
*Proceedings of the IEEE*, 71:941-966, August 1983.
- Rodriguez, B.A., Temes, G.C., et al., “An NMOS Buffer Amplifier,”
*IEEE Trans. on Electron Devices*, Special Corresp., ED-31:203-205, February 1984.
- Temes, G.C. and Haug, K., “Improved Offset-Compensation Schemes for Switched-Capacitor Circuits,”
*Electronics Letters*, 20:508-509, June 1984.
- Watanabe, K. and Temes, G.C., “A Switched-Capacitor Multiplier/Divider with digital and Analog Outputs,”
*IEEE Trans. on Circuits and Systems*, CAS-31:796-800, September 1984.
- Babanezhad, J.N. and Temes, G.C., “A Linear NMOS Depletion Resistor and its Application in an Integrated Amplifier,”
*IEEE J. of Solid-State Circuits*, SC-19:932-938, December 1984.
- Watanabe, K. and Temes, G.C., “A Switched-Capacitor Digital Capacitance Bridge,”
*IEEE Trans. on Instrumentation and Measurements*, IM-33:247-251, December 1984.
- Shyu, J.B., Temes, G.C. and Krumennacher, F., “Random Error Effects in Matched MOS Capacitors and Current Sources,”
*IEEE J. of Solid-State Circuits*, SC-19:948-955, December 1984.
- Shum, D.K. and Temes, G.C., “Stray-Insensitive Differential Input Stages for A/D Convertors,”
*Electronics Letters*, 20:1041-1042, December 1984.
- Orchard, H.J., Temes, G.C., and Cataltepe, T., “Sensitivity Formulas for Terminated Lossless Two-Ports,”
*IEEE Trans. on Circuits and Systems*, CAS-32: 459-466, May 1985.
- Temes, G.C., “High-Accuracy Pipeline A/D Convertor Configuration,”
*Electronics Letters*, 21: 762-763, August 1985.
- Robert, J., Temes, G.C., Krummenacher, I., Valencic, V., and Deval, P., “Offset and Clock-Feedthrough Compensated Switched-Capacitor Integrators,”
*Electronics Letters*, 21: 941-942, September 1985.
- Hsu, T.H. and Temes, G.C., “An Improved Circuit for Pseudo-N-Path Switched-Capacitor Filters,”
*IEEE Trans. on Circuits and Systems*, CAS-32: 1071-1073, October 1985.
- Haug, K., Maloberti, F., Temes, G.C., “Switched-Capacitor Integrators with Low Finite-Gain Sensitivity,”
*Electronics Letters*, 21: 1156-1157, November 1985.
- Babanezhad, J.N. and Temes, G.C., “A 20-V Four Quadrant CMOS Analog Multiplier,”
*IEEE J. of Solid-State Circuits*, SC-20: 1158-1168, December 1985.
- Temes, G.C., “The Compensation of Amplifier Offset and Finite-Gain Effects in Switched-Capacitor Circuits,” (invited paper)
*Periodica Polytechnica*, 1986.
- Temes, G.C., “Simple Formula for Estimation of Minimum Clock Feedthrough Error Voltage,”
*Electronics Letters*, 22: 1069-1070, September 1986.
- Larson, L.E., Temes, G.C., and Law, S., “Comparison of Amplifier Gain Enhancement Techniques for GaAs MESFET Analogue Integrated Circuits,”
*Electronics Letters*, 22: 1138-1139, October 1986.
- Larson, L.E. and Temes, G.C., “Switched-Capacitor Gain Stage with Reduced Sensitivity to Finite Amplifier Gain and Offset Voltage,”
*Electronics Letters*, 22: 1281-1283, November 1986.
- Martin, K., Ozcolak, L., Lee, Y.S., and Temes, G.C., “A Differential Switched-Capacitor Amplifier,”
*IEEE J. of Solid-State Circuits*, SC-22: 104-106, February 1987.
- Robert, J., Temes, G.C., Valencic, V., Dessoulavy, R., and Deval, P., “A 16-Bit Low-Voltage CMOS A/D Converter,”
*IEEE J. of Solid-State Circuits*, SC-22: 157-163, April 1987.
- Temes, G.C. and Ki, W.H., “Fast CMOS Current Amplifier and Buffer Stage,”
*Electronics Letters*, 23: 696-697, June 1987.
- Larson, L.E., Martin, K.W., and Temes, G.C., “GaAs Switched-Capacitor Circuits for High-Speed Signal Processing,”
*J. of Solid-State Circuits*, SC-22: 971-981, December 1987.
- Kunsagi, L. and Temes, G.C., “Buffer-Based Switched-Capacitor Gain Stages,”
*Electronics Letters*, 24: 254-255, March 1988.
- Larson, L.E., Cataltepe, T., and Temes, G.C., “Multibit Oversampled ΣΔ A/D Converter with Digital Error Correction,”
*Electronics Letters*, 24: 1051-1052, August 1988.
- Wang, F.J. and Temes, G.C., “A Fast Offset-Free Sample-and-Hold Circuit,”
*J. of Solid-State Circuits*, SC-23: 1270-1272 (Corr.), October 1988.
- Ki, W.H. and Temes, G.C., “Switched-Capacitor Modulator Circuits,”
*Electronics Letters*, 25: 379-381, March 1989.
- Wang, F.J., Temes, G.C., and Law, S., “A Quasi-Passive CMOS Pipelined D/A Converter,”
*J. of Solid-State Circuits*, SC-24: 1752-1755 (Corr.), December 1989.
- Watanabe, K., Temes, G.C., and Tagami, T., “A New Algorithm for Cyclic and Pipeline Data Conversion,”
*IEEE Trans. on Circuits and Systems*, 37: 249-252, February 1990.
- Hadidi, K., Tso, V., and Temes, G.C., “An 8-b 1.3 MHz Successive-Approximation A/D Converter,”
*J. of Solid-State Circuits*, SC-25: 880-885 (Corr.), June 1990.
- Ki, W.H. and Temes, G.C., “Low-Phase-Error Offset-Compensated Switched-Capacitor Integrator,”
*Electronics Letters*, 26: 957-959, June 1990.
- Zhang, Z. and Temes, G.C., “Multibit Oversampled ΣΔ A/D Convertor with Nonuniform Quantization,”
*Electronics Letters*, 27:528-529, March 1991.
- Comino, V., Steyaert, M.S.J., and Temes, G.C., “A First-Order Current-Steering Sigma-Delta Modulator,”
*IEEE J. of Solid-State Circuits*, SC-26:176-183, March 1991.
- Hairapetian, A., Temes, G.C., and Zhang, Z., “Multibit Sigma-Delta Modulator with Reduced Sensitivity to DAC Nonlinearity,”
*Electronics Letters*, 27:990-991, May 1991.
- Czarnul, Z., Temes, G.C., and Yesilyurt, A.G., “Pseudo-N-Path Switched-Capacitor Filters with Out-of-Band Noise Peaks,”
*Electronics Letters*, 27:1137-1139, June 1991.
- Zhang, Z.X., Temes, G.C., and Czarnul, Z., “Bandpass ΔΣ A/D Convertor Using Two-Path Multibit Structure,”
*Electronics Letters*, 27:2008-2009, October 1991.
- Czarnul, Z., Yesilyurt, A.G., and Temes, G.C., “Multiplexed Noise Shaping Structures for Delta-Sigma Modulators,”
*Electronics Letters*, 27:2342-2343, December 1991.
- Xu, X. and Temes, G.C., “Dual-Truncation ΔΣ Digital-to-Analogue Convertors,”
*Electronics Letters*, 28:92-94, January 1992.
- Abdennadher, S., Kiaei, S., Temes, C.G., and Schreier, R., “Adaptive Self-Calibrating ΔΣ Modulators,”
*Electronics Letters*, 28:1288-1289, July 1992.
- Yang, Y., Schreier, R., Temes, G.C., and Kiaei, S., “On-Line Adaptive Digital Correction of Dual-Quantization ΔΣ Modulators,”
*Electronics Letters*, 28:1511-1513, July 1992.
- Hadidi, K. and Temes, G.C., “Error Analysis in Pipeline A/D Converters and Its Applications,”
*IEEE Trans. on Circuits and Systems*, II, 39:506-515, August 1992.
- Sarhang-Nejad, M. and Temes, G.C., “A High-Resolution Multi-Bit ΣΔ ADC with Digital Correction and Relaxed Amplifier Requirements,”
*IEEE J. of Solid-State Circuits*, SC-28:648-660, June 1993.
- Cao, Y.M. and Temes, G.C., “High-Accuracy Circuits for On-Chip Capacitance Ratio Testing or Sensor Readout,”
*IEEE Trans. on Circuits and Systems*, II, 41:637-639, September 1994.
- Kenney, J.G, Rangan, G., Ramamurthy, K., and Temes, G.C., “An Enhanced Slew Rate Source Follower,”
*IEEE J. of Solid-State Circuits*, SC-30:144-146, February 1995.
- Ki, W.-H. and Temes, G.C., “Optimal Capacitance Assignment of Switched-Capacitor Biquads,”
*IEEE Trans. on Circuits and Systems*, I, 42:334-342, June 1995.
- Temes, G.C., Huang, Y., and Ferguson, Jr., P.F., “A High-Frequency Track-and-Hold Stage with Offset and Gain Compensation,”
*IEEE Trans. on Circuits and Systems*, II, 42:559-561, August 1995.
- Enz, Ch. and Temes, G.C., “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling and Chopper Stabilization,” invited paper,
*Proc. IEEE*, 84:1584-1614, November 1996.
- Yoshizawa, H., Huang, Y., and Temes, G.C., “Improved SC Amplifiers with Low Sensitivity to Op-Amp Imperfections,”
*Electronics Letters*, 33:348-349, February 1997.
- Huang, Y., Ferguson, Jr., P.F., and Temes, G.C., “Reduced Nonlinear Distortion in Circuits with Correlated Double Sampling,”
*IEEE Trans. on Circuits and Systems*, II, 44:593-597, July 1997.
- Wang, B., Kajita, T., Sun, T., and Temes, G.C., “High-Accuracy Circuits for On-Chip Capacitive Ratio Testing and Sensor Readout,”
*IEEE Trans. on Instrumentation and Measurement*, 47:16-20, February 1998.
- Steensgaard, J., Moon, U., and Temes, G.C., “Mismatch-Shaping Switching for Two-Capacitor DAC,”
*Electronics Letters*, 34:1633-1634, August 1998.
- Yoshizawa, H., Huang, Y., Ferguson, P., and Temes, G.C., “MOSFET-Only Switched-Capacitor Circuits in Digital CMOS Technology,”
*IEEE J. of Solid-State Circuits*, 34(6):734-747, June 1999.
- Basu, S. and Temes, G., “Simplified Clock Voltage Doubler,”
*Electron. Lett.*, 35(22):1901-1902, October 28, 1999.
- Moon, U.K., Silva, J., Steensgaard, J. and Temes, G.C., “Switched-Capacitor DAC with Analogue Mismatch Correction,”
*Electron. Lett.*, 35:1903-1904, October 28, 1999.
- Moon, U., Steensgaard, J., and Temes, G., “Digital Techniques for Improving the Accuracy of Data Converters,”
*IEEE Comm. Magazine*, pp. 136-143, October 1999.
- Cauwenberghs, G. and Temes, G.C., “Adaptive Digital Correction of Analog Errors in MASH ADCs - Part I: Off-Line and Blind On-Line Calibration,”
*IEEE Trans. on Circuits and Systems, II*, 47(7): 621-628, July 2000.
- Kiss, P., Silva, J., Weisbauer, A., Sun, T., Moon, U., Stonick, J., and Temes, G., “Adaptive Digital Correction of Analog Errors in MASH ADCs--Part II: Correction Using Test-Signal Injection,”
*IEEE Trans. Circuits and Systems* II, 47(7): 629-638, July 2000.
- Kiss, P., Moon, U., Steensgaard, J., Stonick, J., and Temes, G., “High-Speed ΔΣ ADC with Error Correction,”
*Electron. Lett.*, 37(2): 76-66, January 18, 2001.
- Kajita, T., Temes, G., and Moon, U., “Correlated Double Sampling Integrator Insensitive to Parasitic Capacitance,”
*Electron. Lett.*, 37(3): 151-153, February 1, 2001.
- Keskin, M., Moon, U., and Temes, G., “Switched-Capacitor Resonator Structure with Improved Performance,”
*Electron. Lett.*, 37(4): 212-213, February 15, 2001.
- Wang, X., Kiss, P., Moon, U., Steensgaard, J., and Temes, G., “Digital Estimation and Correction of DAC Errors in Multibit ΔΣ ADCs,”
*Electron. Lett.*, 37(7): 414-415, March 29, 2001.
- Silva, J., Moon, U., Steensgaard, J., and Temes, G., “Wideband Low-Distortion ΔΣ ADC Topology,”
*Electron. Lett.*, 37(12): 737-738, June 7, 2001.
- Keskin, M., Keskin, N., and Temes, G.C., “An Efficient and Accurate DC Analysis Technique for SC Circuits,”
*Analog Int. Circuits & Sig. Proc.*, 30: 239-242, March 2002.
- Keskin, M., Moon, U., and Temes, G.C., “Direct-Charge-Transfer Pseudo-N-Path SC Circuit Insensitive to Element Mismatch and Opamp Nonidealities,”
*Analog. Int. Circuits & Sig. Proc.*, 30: 243-247, March 2002.
- Kajita, T., Moon, U., and Temes, G., “A Noise-Shaping Accelerometer Interface Circuit for Two-Chip Implementation,”
*VLSI Design*, pp. 355-361, June 2002.
- Keskin, M., Moon, U., and Temes, G.C., “A 1-V 10-MHz Clock-Rate 13-Bit CMOS Delta-Sigma Modulator Using Unity-Gain-Reset Opamps,”
*IEEE J. Solid-State Circuits*, 37(7): 817-824, July 2002.
- Kajita, T., Moon, U., and Temes, G.C., “A Two-Chip Interface for a MEMS Accelerometer,”
*IEEE Trans. Instr. & Meas.*, 51(4): 853-858, August 2002.
- Markus, J. and Temes, G.C., “An Efficient Delta-Sigma ADC Architecture for Low Oversampling Ratios,”
*IEEE Trans. Circuits and Sys.-I*, 51(1): 63-71, Jan. 2004.
- Markus, J., Silva, J. and Temes, G.C., “Theory and Applications of Incremental Delta-Sigma Converters,”
*IEEE Trans. Circuits and Sys.-I*, 51(4): 678-690, April 2004.
- Temes, G. and Silva, J., “A Simple and Efficient Noise Estimation Algorithm,”
*Electron. Lett.*, 40(11):640-642, May 27, 2004.
- Rao, A., McIntyre, W., Moon, U. and Temes, G.C., “Noise-Shaping Techniques Applied to Switched-Capacitor Voltage Regulators,”
*IEEE J. Solid-State Circuits*, 40(2):422-429, Febr. 2005.
- Sharma, V., Narayan, A., Rengachari, T., Temes, G., Chaplen, F., Temes, G. and Moon, U., “A Low-Cost Portable Generic Cytosensor for Environmental Monitoring Applications,”
*Biosensors and Bioelectronics*, 20, pp. 2218-2227, May 2005.
- Ahn, G., Chang, D., Brown, M., Ozaki,, N., Youra, H., Yamamura, K., Hamashita, K., Temes, G. and Moon, U., “A 0.6 V 82 dB Delta-Sigma Audio ADC Using Switched-RC Integrators,”
*IEEE J. Solid-State Circuits*, 40(12), pp. 2398-2407, Dec. 2005.
- Schreier, R., Steensgaard, J. and Temes, G., “Design-Oriented Estimation of Thermal Noise in Switched-Capacitor Circuits,”
*IEEE Trans. on Circuits and Sys.-I*, 52(11), pp. 2358-2378, Nov. 2005.
- Wang, R. and Temes, G., “Split-Set Data-Weighted Averaging,”
*IEE El. Letters*, 42(4), pp. 248-249, Febr. 16, 2006.
- Nishida, Y. and Temes, G.C., “Correlated Double Sampling Technique for Continuous-Time Filters,”
*IEE El. Letters*, 42(13), pp. 727-728, June 22, 2006.
- Lee, K. and Temes, G.C., “Enhanced Split-Architecture Delta-Sigma ADC,”
*IEE El. Letters*, 42(13), pp. 737-739, June 22, 2006.
- Maghari, N., Kwon, S., Temes, G.C. and Moon, U., “Sturdy MASH Delta-Sigma Modulator,”
*IEE El. Letters*, 42(22), pp. 1269-1270, Oct. 26, 2006.
- Lee, K., Bonu, M. and Temes, G.C., “Noise-Coupled Delta-Sigma ADCs,”
*IEE El. Letters*, 42(24), pp. 1381-1382, Nov. 23, 2006.
- Quiquempoix, V., Deval, Ph., Barreto, A., Bellini, G., Collings, J., Markus, J., Silva, J. and Temes, G., “A Low-Power 22-Bit Incremental ADC,”
*IEEE J. of Solid-State Circuits*, 41(7), pp. 1562-1571, July 2006.
- Han, J., von Jouanne, A. and Temes, G., “A New Approach to Reducing Output Ripple in Switched-Capacitor- Based Step-Down DC-DC Converters,”
*IEEE Trans. on Power Electronics*, 21(6), pp. 1548-1555, Nov. 2006.
- Yoshizawa, H. and Temes, G., “Switched-Capacitor Track-and-Hold Amplifier with Low Sensitivity to Op-Amp Imperfections,”
*Analog Integrated Circuits and Signal Processing* , 48(3), pp. 267-270, Sept. 2006.
- Wang, Y. and Temes, G.C., “Dynamic Biasing Scheme for High-Speed Low-Voltage Switched-Capacitor Stages,”
*IEE El. Letters*, 43(4), pp. 214-216, Febr. 15, 2007.
- Yoshizawa, H. and Temes, G.C., “Switched-capacitor Track-and-Hold Amplifiers with Low Sensitivity to Op-amp Imperfections,”
*IEEE Trans. on Circuits and Systems-I*, 54(1), pp. 193-199, Jan. 2007.
- Kurahashi, P., Hanumolu, P., Temes, G. and Moon, U., "A 0.6V Highly Linear Switched-R-MOSFET-C Filter,"
*IEEE J. of Solid-State Circuits*, 42(8), pp. 1699-1709, Aug. 2007.
- Wang. R., Moon, U. and Temes, G.C., “A 100-dB Gain-Corrected Delta-Sigma Audio DAC with Headphone Driver,”
*Analog Integrated Circuits and Signal Processing*, 51(1), pp. 27-32, April 2007.
- Lee, K., Chae, J. and Temes, G.C., “Efficient Floating Double-Sampling Integrator for DS ADCs,”
*Electronics Letters*, 43(25), pp. 1413-1414, Dec.6, 2007.
- Kim, M., Ahn, G., Hanumolu, P., Lee, S., Kim, S., You, S., Kim, J., Temes, G.C. and Moon, U. “A 0.9V 92dB Double-Sampled Switched-RC Delta-Sigma Audio ADC,”
*IEEE J. of Solid-State Circuits*, 43(5), pp. 1195-1206, May 2008.
- Steensgaard, J., Zhang, Z., Yu, W., Sarhegyi, A. Lucchese, L., Kim, D., and Temes, G.C., “Noise-Power Optimization of Incremental Data Converters,”
*IEEE Trans. on Circuits and Systems- I*, vol. 55, no. 5, pp. 1289-1296, June 2008.
- Lee, K. and Temes, G.C., “Enhanced Split-Architecture Delta-Sigma ADC,”
*Analog Integrated Circuits and Signal Processing*, 56(3), pp. 251-257, Sept. 2008.
- Lee, K., Chae, J., Aniya, M., Hamashita, K. Takasuka, K., Takeuchi, S., Temes, G.C “A Noise-Coupled Delta-Sigma ADC with 4.2 MHz Bandwidth, -98 dB THD and 79 dB SNDR,”
*IEEE J. of Solid-State Circuits*, 43(12), pp. 2601-2612, Dec. 2008.
- Maghari, N., Temes, G.C and Moon, U, “Single-Loop Delta-Sigma Modulator with Extended Dynamic Range,”
*El. Letters*, 44(25), pp. 1452-1453, Dec.4, 2008.
- Wang, Y. and Temes, G.C., “Noise-Coupled Continuous-Time Delta-Sigma ADCs,”
*El. Letters*, 45(6), pp. 349-352, March 12, 2009.
- Lee. K., Miller, M. and Temes, G.C., “An 8.1 mW, 82 dB Delta-Sigma ADC with 1.9 MHz BW and -98 dB THD,”
*IEEE J. of Solid-State Circuits*, 44(8), pp. 2202-2211, Aug. 2009.
- Zhang, Z., Steensgaard, J., Temes, G.C. and Wu, J., “A 14-Bit Dual-Path 2-0 MASH ADC with Dual Digital Error Correction,”
*Analog Integrated Circuits and Signal Processing*, 59(2), pp. 143-150, May 2009.
- Lee, K., Meng, Q., Sugimoto, T., Hamashita, K., Takasuka, K., Takeuchi, S., Moon, U. and Temes, G., “A 0.8V, 2.6 mW, 88dB Dual-Channel Audio Delta-Sigma DAC with Headphone Driver,"
*IEEE J. of Solid-State Circuits*, 44(3), pp. 916-927, March 2009.
- Lee, K. and Temes, G.C., “Improved Architecture for Low-Distortion Delta-Sigma ADCs,”
*El. Letters*, 45(14), pp. 730-731, July 2, 2009.
- Maghari, N.,Temes, G.C. and Moon, U., “Noise-Shaped Integrating Quantizers in Delta-Sigma Modulators,”
*El. Letters*, 45(12), June 4, 2009.
- Shen, W. and Temes, G.C.,”Double-Sampled Delta-Sigma Modulator with Relaxed Feedback Timing,”
*El. Letters*, 45(17), pp. 875-877, Aug. 18, 2009.
- Yu, W. and Temes, G.C., “Power-Up Calibration Techniques for Double-Sampled Delta-Sigma Modulators,”
*El. Letters*, 45(19), Sept. 18, 2009.
- Yu, W., Lin, J. and Temes, G.C., “Two-Step Split-Junction SAR ADC,”
*El. Letters*, 46(3), pp. 211-212, Febr. 4, 2010.
- Wang, T. and Temes, G.C., “Switched-R Tuning Technique for Gm-C Filters,”
*El. Letters*, 46(4), pp. 275-276, Febr. 18, 2010.
- Wang, Y., Hamashita, K. and Temes, G.C., “Hybrid Delta-Sigma ADC,”
*Analog Integrated Circuits and Signal Processing*, 63(2), pp. 293-296, May 2010.
- Temes, G.C., “Micro-Power Data Converters: a Tutorial,”
*IEEE Trans. on Circuits and Systems – II*, (57)6, pp. 405-410, June 2010.
- Nishida, Y. Hamashita, K. and Temes, G.C., “An Enhanced Dual-Path Delta-Sigma A/D Converter,”
*IEICE Trans. on Electronics*, E93-C(6), pp. 884-892, June 2010.
- Wang, T. and Temes, G.C., “Low-Power Parasitic-Insensitive Switched-Capacitor Integrator for Delta-Sigma ADCs,”
*El. Letters*, 46(16), pp. 1114-1116, Aug. 5, 2010.
- Chae, J. and Temes, G.C., “Comparator-Based Buffer with Resistive Error Correction,”
*El. Letters*, 46(17), pp. 1188-1190, Aug. 19, 2010.
- Lin, J., Yu, W. and Temes, G.C.,”Multi-Step Capacitor-Splitting SAR ADC,”
*El. Letters*, 46(21), pp. 1426-1428, Oct. 14, 2010.
- Jung, Y., Lee, S., Chae, J. and Temes, G.C., “Low-Power and Low-Offset Comparator Using Latch Load,”
*El. Letters*, 47(3), pp. 167-168, 2011.
- Yoshizawa, H., Yabe, T. and G.C. Temes, “High-Precision Switched-Capacitor Integrator Using Low-Gain Opamp,”
*El. Letters*, 47(5), 2011.
- Wang, Y., Hanumolu, K. and Temes, G.C., “Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs with Extra Loop Delay,”
*IEEE Trans. on Circuits and Systems – I*, (58)7, pp. 1518-1530, July 2011.
- Tong, T., Hanumolu, P.K. and Temes, G.C., “A Semi-Synchronous SAR ADC,”
*Analog Integrated Circuits and Signal Processing*, 71(3), pp. 407-410, June 2012.
- Jung, Y., Lee,S., Chen, C.-H. and Temes, G.C., “Double Noise Coupling ΔΣ Analogue-to-Digital Converter,”
*Electronics Letters*, vol. 48, no. 10, pp. 557-558, May 2012.
- Wei Li, Tao Wang, J. Cao and Gabor C. Temes, “Teraohm On-Chip Resistance Realization Using Switched Capacitor Topologies,”
*Electronic Letters*, vol. 48, no. 11, pp. 623–624, May 2012.
- Yu, W. and Temes, G.C., “A Digital DAC Calibration Technique for ΔΣ and Incremental Modulators,”
*Electronics Letters*, vol.48, no.13, pp. 754-755, June 2012.
- Meng, X., Wang, T. and Temes, G.C., “Charge Compensation Technique for Switched-Capacitor Circuits,”
*Electronic Letters*, vol. 48, no. 16, pp. 988-990, August 2012.
- Zanbaghi, R., Saxena, S., Temes, G.C. and Fiez, T.S., “A 75 dB SNDR, 10 MHz Conversion Bandwidth Stage-Shared 2-2 Mash ΔΣ Modulator Dissipating 9 mW,”
*IEEE Trans. on Circuits and Systems – I*, vol. 59, no. 8, pp. 1614-1625, Aug. 2012.
- Tong, T., Yu, W., Hanumolu, P.K. and Temes, G.C., “Calibration Techniques for SAR ADCs,”
*Analog Integrated Circuits and Signal Processing*, 73(1), pp. 301-309, October 2012
- Zhang, Y., Chia-Hung Chen and Gabor C. Temes, “Accuracy-enhanced switched-capacitor stages using low-gain opamps,”
*Electronic Letters*, vol. 49, no. 1, pp. 22-23, Jan 2013.
- Chen, C-H., Y. Jung, J. L. Ceballos, and G. C. Temes. “Multi-step extended-counting analogue-to-digital converters,”
*Electronics Letters*, vol. 49, no. 1 (2013): 30-31.
- Chen, C. H., Y. Zhang, J. L. Ceballos, and G. C. Temes. “Noise-shaping SAR ADC using three capacitors,”
*Electronics Letters*, vol. 49, no. 3 (2013): 182-184.
- Chen, C-H., Y. Zhang, Y. Jung, T. He, J. L. Ceballos, and G. C. Temes, “Two-step incremental analogue-to-digital converter,”
*Electronics Letters*, vol. 49, no. 4 (2013): 250-251.
- Zhang, Y., Chen, C. H. and Temes, G. C., “An efficient technique for excess loop delay compensation in continuous-time ΔΣ modulators,”
*Electronics Letters*, vol. 49, no. 24 (2013) 1522-1523.
- Meng, X and Temes, G.C., “Double-sampled wideband delta-sigma ADCs with shifted loop delays,”
*Electronics Letters*, vol. 50, no. 11 (2014), 794-795.
- Meng, X, Zhang, Y., He, T. and Temes, G.C., “Low-distortion wideband delta-sigma ADCs with shifted loop delays,”
*IEEE Trans. on Circuits and Systems – I*, (62)2, 376-384. Febr. 2015.
- Chen, C-H, Zhang , Y., He, T., Chiang, P.Y. and Temes, G.C., “A micro-power two-step incremental analog-to-digital converter,”
*IEEE J. of Solid-State Circuits*, vol. 50, no. 8, Aug. 2015, pp. 1796-1808.
- Zhang, Y., Chen, C. H. He, T. and Temes, G. C., “A continuous-time ΔΣ modulator for biomedical ultrasound beamformer using digital ELD compensation and FIR feedback,”
*IEEE Trans. on Circuits and Systems – I*, vol. 62, no. 7, July 2015, pp. 1689-1698.
- Chen, C-H, Zhang , Y., He, T. and Temes, G.C., “A two-step multi-stage incremental analog-to-digital converter,”
*El. Letters*, vol. 51, no. 24, pp. 1975-1977, Nov. 2015.
- Chen, C-H, Zhang , Y., He, T. and Temes, G.C., “Incremental analog-to-digital converters for high-resolution energy-efficient sensor interfaces,”
*IEEE J. of Emerging and Selected Topics in Circuits and Systems*, vol. 5, no. 4, pp. 612-623, Dec. 2015.
- He, T., Chen, C-H, Zhang, Y. and Temes, G.C., “Digital ELD compensation techniques with embedded truncator for continuous-time delta-sigma modulators,”
*El. Letters*, vol. 52, no. 1, pp. 20-21, Jan. 2016.
- Zhang, Y., He, T., Chen and Temes, G.C., “Multi-step incremental ADC with extended binary counting,”
*El. Letters*, vol. 52, 2016, Volume: 52, no.9, pp 697–699.
- Payandehnia, P., Maghami, H., Kareppagoudr, M. and Temes, G.C., “A passive switched-capacitor filter with complex poles for high-speed applications,”
* Electronics Letters*, 2016, vol. 52, no.19, pp. 1592–1594.
- Zhang, Y.,C-H Chen, He, T. and G.C. Temes, “A 16-bit multi-step Incremental ADC with single-opamp multi-slope extended counting,”
*IEEE J. of Solid-State Circuits*, vol. 52, no. 4, April 2017, pp. 1066 - 1076.
- Jung, Y. and Temes, G.C. “A wide-band high-accuracy incremental ADC,”
*Analog Integrated Circuits and Signal Processing*, Febr. 2017, vol. 90, no. 2, pp. 291 - 300.
- Payandehnia, P. and Temes, G.C., “Fully Passive 3rd-Order Noise Shaping SAR ADC,”
*Electronics Letters, *Apr. 13,2017, vol. 53, no. 8. pp. 528 – 530.
- Jung, Y. and Temes, G.C., “Power-efficient noise-coupled ΔΣ ADC with simple delay cells,”
*El. Letters, *May 25, 2017, vol. 53, no. 11, pp. 712-713.
- Jung, Y. and Temes, G.C. “Improved double noise coupling ΔΣ ADC,
*Analog Integrated Circuits and Signal Processing*, vol. 91, no. 3, June 2017.
- Sadollahi, M., Hamashita, K. Sobue, K. and Temes, G.C., “An 11-bit 250 nW 10 kS/s SAR ADC with doubled input range for biomedical applications,” IEEE Transactions on Circuits and Systems-I, to appear.
- Wang, Y., He, T., Silva, P., Zhang, Y. and Temes, G.C., “Wide-band high-accuracy ΔΣ ADC using segmented DAC with DWA and mismatch shaping,”
*El. Letters*, 2017,vol. 53, no.11, pp. 713-714.

#### Conference Proceedings

- Temes, G.C., “Interaction Between the Energy-Losses of Protons in Free Electron Gas,” KFKI Kozlemenyek,
*Proc. of the Central Research Inst. of Physics*, Budapest, 1957, 5:77-83.
- Temes, G.C., Boire, P., and Banfill, H., “A New Brightness Meter,”
*Proc. of the Instrument Soc. of America*, June 1960, pp. 6-1 to 6-8.
- Temes, G.C., “A Method for the Estimation and Precorrection of Losses in Terminated LC Networks,”
*Proc. of the Natl. Electronics Conf.*, sponsored by AIEE, October 9-11, 1961, Chicago, 17:98-110.
- Temes, G.C., “Filter Synthesis Using a Digital Computer,”
*1962 Inst. of Radio Engineers Int. Convention Record*, sponsored by IRE Professional Group on Circuit Theory, March 29, 1962, New York, 9:211-227.
- Temes, G.C., “An Extension of Darlington's Semiuniform Predistortion Procedure,”
*Proc. of the 1st Annual Allerton Conf. on Circuit & System Theory*, sponsored by Department of Electrical Engineering and Coordinated Science Lab., November 15-17, 1963, University of Illinois, 1:246-258.
- Smith, B.R. and Temes, G.C., “An Iterative Approximation Procedure for Automatic Filter Synthesis,
*IEEE Int. Convention Record*, 1964, sponsored by IEEE, Inc., March 23-26, 1964, New York, 12:270-281, pt. 1.
- Temes, G.C. and Bingham, J.A.C., “Iterative Chebyshev Approximation for Network Synthesis,”
*Proc. of the Allerton Conf. on Circuit and System Theory*, IEEE Circuit Theory group and the University of Illinois, October 20-22, 1965, 3:773-785.
- Temes, G.C., “Iterative Optimization Techniques,”
*Proc. of the Inst. of Modern Solid-State Circuit Design*, sponsored by University of Santa Clara and NASA, September 15-16, 1966, 1:96-114.
- Temes, G.C. and Orchard, H.J., “Maximally Flat Approximation Techniques,”
*Proc. of the Allerton Conf. on Circuit and System Theory*, University of Illinois, November 1966, 4:465.
- Temes, G.C. and Gyi, M., “Design of Filters with Arbitrary Passband and Chebyshev Stopband Attenuation,”
*1967 IEEE Int. Convention Record*, March 1967, 15(5):2-12.
- Temes, G.C., “Bandlimited System with Optimum Time Response,”
*7th Annual Proc. of the Allerton Conf. on Circuit and System Theory*, sponsored by Circuit Theory and Automatic Control Groups of the IEE, October 8-10, 1969, University of Illinois, pp. 805-818.
- Temes, G.C., “Computer Synthesis and Optimization of Filters,” Abstract,
*3rd Asilomar Conf. Record on Circuits and Systems*, sponsored by IEEE Groups on Circuit Theory and Automatic Control, December 10-12, 1969, p. 293.
- Temes, G.C., “Automated Circuit Design,” Abstract,
*Proc. of 1970 Chiao Tung Colloquium on Circuits & Systems*, August 25-26, 1970, Taiwan, p. 291.
- Marshall F.C. and Temes, G.C., “Computer-Aided Chebyshev Optimization in the Time Domain,”
*Proc. of the Kyoto Int. Conf. on Circuit and System Theory*, sponsored by Inst. of Electronics and Communication Engineers of Japan, September 9-11, 1970, pp. 13-14.
- Gadenz, R.N. and Temes, G.C., “Statistical Transient Analysis of Nonlinear Circuits,”
*Proc. Mexico Int. IEEE Conf. on systems, Networks and Computers*, January 19-21, 1971, Oaxtepec, Mexico.
- Barcilon, V. and Temes, G.C., “On Bandwidth, Risetime and Overshoot,”
*Proc. of the London 1971 IEEE Int. Symposium on Electrical Network Theory*, The Circuit Theory Group and the UK and RI Section of IEEE, September 6-10, 1971, City University, London, England, pp. 39-40.
- Temes, G.C., Kurtz, J., and Orchard, H.J., “Least Squares Passband Filters,”
*Proc. of the London 1971 IEEE Int. Symposium on Electrical Network Theory*, September 6-10, 1971, City University, London, England, pp. 111-112.
- Temes, G.C., Ebers, R.M., and Gadenz, R.N., “Some Novel Applications of the Adjoint Network Concept in Frequency-Domain Circuit Analysis and Optimization,
*Proc. of the London 1971 IEEE Int. Symposium on Electrical Network Theory*, September 6-10, 1971, City University, London, England, pp. 111-112.
- Gadenz, R.N. and Temes, G.C., “A Computational Algorithm for the Design of Elliptic Filters,”
*Proc. of the 1972 Int. Filter Symposium*, sponsored by NSF, University of Maryland, and UCLA, April 5-18, 1972, Santa Monica, CA, pp. 28-29.
- Temes, G.C. and Orchard, H.J., “Sensitivity and Reflection Coefficients,
*Proc. of the 1972 Int. Filter Symposium*, sponsored by NSF, University of Maryland, and UCLA, April 5-18, 1972, Santa Monica, CA, pp. 92-93.
- Gadenz, R.N. and Temes, G.C., “Efficient Hybrid and State-Space Analysis of the Adjoint Network,”
*Proc. of the 1972 Int. Symposium on Circuit Theory*, sponsored by IEEE, April 18-22, 1972, Los Angeles, pp. 184-188.
- Barcilon, V. and Temes, G.C., “Recent Results in the Optimization of Bandlimited Systems,”
*Proc. of the 1973 Int. Symposium on Circuit Theory*, Sponsored by IEEE, April 9-11, 1973, Toronto, Canada, pp. 194-197.
- Gadenz, R.N., Rezai-Fakhr, G., and Temes, G.C., “A Method for the Computation of Large Tolerance Effects,”
*Proc. of the 1973 Int. Symposium on Circuit Theory*, sponsored by IEEE, April 9-11, 1973, Toronto, Canada, pp. 220-222.
- Orchard, H.J. and Temes, G.C., “Vestigial Sideband Filters,”
*1974 European Conf. on Circuit Theory and Design*, July 23-26, 1974, London, England, pp. 26-31.
- Rezai-Fakhr, M.G. and Temes, G.C., “Statistical Large-Tolerance Analysis of Linear and Nonlinear Circuits in the Time Domain,”
*1974 European Conf. on Circuit Theory and Design*, July 23-26, 1974, London, England, pp. 295-300.
- Temes, G.C. and Marshall, F.C., “Window Functions for the Fast Fourier Transform,”
*Proc. of the II Interamerican Conf. on Syst. and Inf.*, November 1974, Mexico City.
- Babic, H. and Temes, G.C., “Optimum Low-Order Discrete Windows for the Estimation of Power Spectra,”
*Proc. of the 3rd Int. Symposium on Network Theory*, September 1-5, 1975, Split, Yugoslavia, pp. 745-757.
- Temes, G.C., “A Worst-Case Error Analysis for the FFT,”
*Proc. of the 1976 IEEE Int. Symposium on Circuits & Systems*, April 27-29, 1976, Munich, W. Germany, pp. 98-101.
- Temes, G.C., “Efficient Methods of Fault Analysis,”
*Proc. of the 20th Midwest Symposium on Circuits and Systems*, August 1977, Lubbock, TX, pp. 191-194.
- Temes, G.C., “Efficient Methods of Fault Analysis,”
*Proc. of the 4th Symposium on Reliability in Electronics*, October 1977, Budapest, Hungary, pp. 241-248.
- Temes, G.C. and Cheung, D.T., “Integrated Input Circuits for Photo Detectors,”
*Proc. of the 11th Asilomar Conf. on Circuits, Systems & Computers*, November 1977, Pacific Grove, CA, pp. 451-455.
- Cho, K.M. and Temes, G.C., “Real-Factor FFT Algorithms,”
*Proc. of the 1978 Int. Conf. on Acoustics, Speech & Signal Processing*, April 1978, Tulsa, OK, pp. 634-637.
- Temes, G.C., “Digital-Filter Design Techniques for the Synthesis of Switched-Capacitor Active Circuits,”
*Proc. of the 1978 Int. Conf. on Digital Signal Processing*, August 1978, Florence, Italy, pp. 569-577.
- Orchard, H.J. and Temes, G.C., “Spectral Analysis of Switched-Capacitor Filters Designed Using the Bilinear z-Transform,”
*Proc. of the 12th Annual Asilomar Conf. on Circuits, Systems, and Computers*, November 1978, pp. 674-678.
- Young, I.A., Simonyi, A., and Temes, G.C., “Switched-Capacitor Filter Sections Implementing the Bilinear z-Transform,”
*Proc. of the 12th Annual Asilomar Conf. on Circuits, Systems and Computers*, November 1978, pp. 689-692.
- Szentirmai, G. and Temes, G.C., “Switched-Capacitor Building Blocks,”
*Proc. of the 13th Annual Asilomar Conf. on Circuits, Systems and Computers*, November 1979, pp. 542-545.
- Temes, G.C. and Gregorian, R., “Compensation for Parasitic Capacitances in Switched-Capacitor Filters,”
*Proc. of the 13th Annual Asilomar Conf. on Circuits, Systems and Computers*, November 1979, pp. 546-548.
- Gregorian, R. and Temes, G.C., “Self-Equalizing Sample-and-Hold Circuits,
*Proc. of the 13th Annual Asilomar Conf. on Circuits, Systems and Computers*, November 1979, pp. 549-551.
- Nossek, J. and Temes, G.C., “Switched-Capacitor Filter Design Using Bilinear Element Modeling,”
*Proc. of the 1980 Int. Symposium on Circuits and Systems*, April 1980, Houston, TX, pp. 330-333.
- Fan, S.C., Gregorian, R., Temes, G.C., and Zomorrodi, M., “Switched-Capacitor Filters Using Unit-Gain Buffers,”
*Proc. of the 1980 Int. Symposium on Circuits and Systems*, April 1980, Houston, TX, pp. 334-337.
- Lee, M.S., Temes, G.C., Chang, C., and Ghaderi, M.B., “Bilinear Switched-Capacitor Ladder Filters,”
*Proc. of the 14th Asilomar Conf. on Circuits, Systems and Computers*, November 1980, pp. 435-439.
- Muller, G. and Temes, G.C., “A Simple Method for the Computation of the Frequency Response of a Class of Switched-Capacitor Filters,”
*Proc. of the 14th Asilomar Conf. on Circuits, Systems and Computers*, November 1980, pp. 440-442.
- Ghaderi, M.B., Temes, G.C., Lee, M.S., and Chang, C., “Bilinear Switched-Capacitor Ladder Filters - New Results,”
*Proc. of the 1981 IEEE Int. Symposium on Circuits and Systems*, April 1981, Chicago, IL, pp. 170-174 (invited paper).
- Ghaderi, M.B., Temes, G.C., and Nossek, J.A., “Switched-Capacitor Pseudo-N-Path Filters,”
*Proc. of the 1981 IEEE Int. Symposium on Circuits and Systems*, April 1981, Chicago, IL, pp. 519-522 (invited paper).
- Temes, G.C., “Switched-Capacitor Filters,”
*Proc. 24th Midwest Symposium on Circuits and Systems*, June 1981, Albuquerque, NM, pp. 577-578 (invited).
- Temes, G.C., “Switched-Capacitor Filters: History and the State of the Art,”
*Proc. 1981 European Conf. on Circuit Theory and Design*, August 1981, The Hague, Netherlands, pp. 176-185 (invited).
- Temes, G.C. and Mueller, G., “The Poor Man’s Algorithm for the Computer-Aided Analysis of Switched Capacitor Filters,”
*15th Asilomar Conf. on Circuits, Systems, and Computers*, November 9-11, 1981, Pacific Grove, CA.
- Law, S., Temes, G.C., Ngo, T.M., and Ibrahim, A., “A High-Speed CCD Interpolator Filter,”
*IEEE Internat. Conf. on Circuits and Computers*, September 1982, New York, pp. 482-485.
- Hsu, T.H. and Temes, G.C., “Low-Sensitivity Digital Filter Design from a Switched-Capacitor Filter Prototype,”
*1983 IEEE Internat. Symp. on Circuits and Systems*, May 1983, Newport Beach, CA, pp. 282-285.
- Watanabe, K. and Temes, G.C., “A Switched-Capacitor Digital Multiplier,”
*1983 IEEE Internat. Symp. on Circuits and Systems*, Newport Beach, CA, May 1983, pp. 1270-1273.
- Watanabe, K. and Temes, G.C., “A Switched-CapacitorDigitalCapacitanceBridge,”
*Proc. of the 1984 IEEE Internat. Symp. on Circuits and Systems*, May 7-10, 1984, Montreal, Canada, pp. 173-176.
- Orchard, H.J., Temes, G.C., and Cataltepe, T., “General Sensitivity Theorems for Terminated Lossless Two-Ports,”
*Proc. of the 1984 IEEE Internat. Symp. on Circuits and Systems*, May 7-10, 1984, Montreal, Canada, pp. 177-180.
- Haug, K., Temes, G.C., and Martin, K.W., “Improved Offset Compensation Schemes for Switched-Capacitor Circuits,”
*Proc. of the 1984 IEEE Internat. Symp. on Circuits and Systems*, May 7-10, 1984, Montreal, Canada, pp. 1054-1057.
- Babanezhad, J.N. and Temes, G.C., “Linear MOS Simulated Resistors,”
*Proc. of the 1985 IEEE International Symp. on Circuits and Systems*, June 5-7, 1985, Kyoto, Japan, pp. 1419-1422.
- Shyu, J.B., Temes, G.C., and Krummenacher, I., “Random Error Effects in Matched MOS Capacitors and Current Sources,”
*Proc. of the 1985 IEEE International Symp. on Circuits and Systems*, June 5-7, 1985, Kyoto, Japan, pp. 1415-1418.
- Larson, L., Jensen, J., Greiling, P., and Temes, G.C., “GaAs Differential Amplifiers,”
*Techn. Digest of the GaAs IC Symp.*, November 12-14, 1985, Monterey, CA, pp. 19-22.
- Robert, J., Temes, G.C., Krummenacher, F., Valencic, V., and Deval, P., “A Low-Voltage High-Resolution CMOS A/D Converter with Analog Compensation,”
*Proc. of IEEE 1986 Custom IC Circuits Conf.*, May 986, Rochester, NY, pp. 362-365.
- Haug, K., Maloberti, F., and Temes, G.C., “Switched-Capacitor Circuits with Low Op-Amp Gain Sensitivity,”
*Proc. 1986 IEEE International Symp. on Circuits and Systems*, May 1986, San Jose, CA, pp. 797-800.
- Robert, J., Temes, G.C., Krummenacher, F., Valencic, V., and Deval, P., “Offset and Clock Feedthrough Compensated SC Integrators,”
*Proc. 1986 IEEE International Symp. on Circuits and Systems*, May 1986, San Jose, CA, pp. 817-818.
- Babanezhad, J.N. and Temes, G.C., “Analog MOS Computational Circuits,”
*Proc. 1986 IEEE International Symp. on Circuits and Systems*, May 1986, San Jose, CA, pp. 1157-1160.
- Larson, L.E., Martin, K., and Temes, G.C., “GaAs Switched-Capacitor Circuits for Video Signal Processing,”
*Digest of 1987 IEEE International Solid-State Circuits Conf.*, New February 1987, York, pp. 40-41 and 332.
- Larson, L.E. and Temes, G.C., “Switched-CapacitorBuilding Blocks with Reduced Sensitivity to Finite Amplifier Gain, Bandwidth and Offset Voltage,”
*Proc. of 1987 IEEE International Symp. on Circuits and Systems*, May 1987, Philadelphia, PA, pp. 334-338.
- Larson, L.E., Temes, G.C., and Martin, K.W., “Switched-Capacitor Circuits with Reduced Sensitivity to Finite Amplifier Gain, Bandwidth and Offset Voltage,”
*Proc. of European Conf. on Circuit Theory and Design*, September 1987, Paris, France, pp. 543-548.
- Wang, F.J. and Temes, G.C., “A Fast Offset-Free Sample-and-Hold Circuit,”
*Proc. of IEEE Custom Integrated Circuits Conf.*, May 16-19, 1988, Rochester, NY, pp. 5.6.1-5.6.3.
- Wang, F.J., Temes, G.C., and Law, S., “A Quasi-Passive CMOS Pipeline D/A/ Converter,”
*Proc. of IEEE Custom Integrated Circuits Conf.*, May 16-19, 1988, Rochester, NY, pp. 18.1.1-18.1.4.
- Temes, G.C., Martin, K., and Larson, L., “State-of-the-Art and Future Prospects for Analog Signal Processing,”
*Proc. of the IEEE International Symp. on Circuits and Systems*, June 7-9, 1988, Espoo, Finland, pp. 1655-1660.
- Temes, G.C., Wang, F.J., and Watanabe, K., “Novel Pipelined Data Converters,”
*Proc. of the IEEE International Symp. on Circuits and Systems*, June 7-9, 1988, Espoo, Finland, pp. 1943-1946.
- Watanabe, K., Temes, G.C., and Moriuchi, Y., “A New Digital-to-Analog Conversion Algorithm,”
*Proc. of the IEEE International Symp. on Circuits and Systems*, June 7-9, 1988, Espoo, Finland, pp. 2817-2820.
- Cataltepe, T., Kramer, A., Larson, L., Temes, G.C., and Walden, R., “Digitally Corrected Multi-Bit ΣΔ Data Converters,”
*Proc. of the IEEE International Symp. on Circuits and Systems*, May 8-11, 1989, Portland, OR, pp. 647-650.
- Candy, J.C. and Temes, G.C., “Tutorial Discussion of the Oversampling Method for A/D and D/A Conversion,”
*Proc. of the International Symp. on Circuits and Systems Conf.*, May 1-3, 1990, New Orleans, LA, pp. 910-913.
- Walden, R.H., Cataltepe, T., and Temes, G.C., “Architectures for High-Order Multibit ΣΔ Modulators,”
*Proc. of the International Symp. on Circuits and Systems*, May 1-3, 1990, New Orleans, LA, pp. 895-898.
- Hadidi, K., Temes, G.C., and Martin, K.W., “Error Analysis and Digital Correction Algorithms for Pipelined A/D Converters,”
*Proc. of the International Symp. on Circuits and Systems*, May 1-3, 1990, New Orleans, LA, pp. 1709-1712.
- Ki, W.-H. and Temes, G.C., “Offset-Compensated Switched-Capacitor Integrators,”
*Proc. of the International Symp. on Circuits and Systems*, May 1-3, 1990, New Orleans, LA, pp. 2829-2832.
- Hadidi, K., Tso, V.S., and Temes, G.C., “Fast Successive-Approximation A/D Converters,”
*Proc. of the Custom Int. Circuits Conf.*, May 13-16, Boston, MA, 1990, pp. 6.1.1-6.1.4.
- Comino, V., Steyaert, M., and Temes, G.C., “A First-Order Current-Steering Sigma-Delta Modulator,”
*Proc. of the Custom Int. Circuits Conf.*, May 13-16, 1990, Boston, MA, pp. 6.3.1-6.3.4.
- Candy, J.C. and Temes, G.C., “Oversampling Methods for Data Conversion,”
*Proceedings*, IEEE Pacific Rim Conf. on Communications, Computers, and Signal Processing, Victoria, B.C., Canada, May 9-10, 1991, pp. 498-502.
- Liu, C.T., Samueli, H., and Temes, G.C., “FIR Filter Design for Sigma-Delta A/D Converters Using Quadratic Programming,”
*Proceedings*, IEEE Pacific Rim Conf. on Communications, Computers, and Signal Processing, pp. 760-763.
- Powell, S.R., Chan, P.M., and Temes, G.C., “A Ripple Reduction Technique for Digital Filters,”
*Proceedings*, 1991 IEEE Internat. Symp. on Circuits and Systems, Singapore, June 11-14, 1991, pp. 148-151.
- Liu, C.T., Samueli, H., and Temes, G.C., “FIR Filter Design Using Quadratic Programming,”
*Proceedings*, 1991 IEEE Internat. Symp. on Circuits and Systems, Singapore, June 11-14, 1991, pp. 148-151.
- Ki, W.H. and Temes, G.C., “Gain and Offset Compensated Switched-Capacitor Filters,”
*Proceedings*, 1991 IEEE Internat. Symp. on Circuits and Systems, Singapore, June 11-14, 1991, pp. 1561-1564.
- Vital, J.C. and Temes, G.C., “Clock Generation System with Reduced Filter Noise in the Baseband,”
*Proceedings*, 1991 IEEE Internat. Symp. on Circuits and Systems, Singapore, June 11-14, 1991, pp. 2621-2624.
- Hadidi, Kh. and Temes, G.C., “A High-Resolution Low-Offset and High-Speed Comparator,”
*Proceedings*, Custom Int. Circuits Conf., May 3-6, 1992, Boston, MA, pp. 16.1.1-16.1.4.
- Sarhang-Nejad, M. and Temes, G.C., “A True 16-bit 20 kHz Multibit ΣΔ ADC with Digital Correction,”
*Proceedings*, Custom Int. Circuits Conf., May 3-6, 1992, Boston, MA, pp. 16.4.1-16.4.4.
- Czarnul, Z., Temes, G.C., Yesilyurt, A.G., and Zhang, Z., “Bandpass Delta-Sigma A/D Converters with Pseudo-N-Path SC Integrators,”
*Proceedings*, International Symp. on Circuits and Systems, May 10-13, 1992, San Diego, CA, pp. 593-596.
- Xu, X.F. and Temes, G.C., “The Implementation of Dual-Truncation ΣΔ D/A Converters,
*Proceedings*, International Symp. on Circuits and Systems, May 10-13, 1992, San Diego, CA, pp. 597-600.
- Ki, W.-H. and Temes, G. C., “Area-Efficient Gain- and Offset-Compensated Very Large Time Constant SC Biquads,”
*Proceedings*, International Symp. on Circuits and Systems, May 10-13, 1992, San Diego, CA, pp. 1187-1190.
- Czarnul, Z., Yesilyurt, A.G., and Temes, G.C., “Multiplexed Noise Shaping Structures for Delta-Sigma Modulators,”
*Proceedings*, International Symp. on Circuits and Systems, May 10-13, 1992, San Diego, CA, pp. 1308-1311.
- Rangan, G., Kenney, J.G., Ramamurthy, K., and Temes, G.C., “High-Speed Buffers for Op-Amp Characterization,”
*Proceedings*, International Symp. on Circuits and Systems, May 3-6, 1993, Chicago, IL, pp. 994-997.
- Abdennadher, S., Kiaei, S., Yang, Y., and Temes, G.C., “Adaptive Digital Correction for Dual-Quantization Δ-Σ Modulators,”
*Proceedings*, International Symp. on Circuits and Systems, May 3-6, 1993, Chicago, IL, pp. 1228-1230.
- Temes, G.C., Deval, P., and Valencic, V., “SC Circuits: The State of the Art Compared to SI Techniques,”
*Proceedings*, International Symp. on Circuits and Systems, May 3-6, 1993, Chicago, IL, pp. 1231-1234.
- Temes, G.C., “Sigma-Delta Data Converter Architectures with Multibit Internal Quantizers,”
*Proceedings*, European Conf. on Circuit Theory and Design, August 30-September 3, 1993, Davos, Switzerland.
- Hadidi, K. and Temes, G.C., “A Novel Input Differential Pair for Improved Linearity Buffer and S/H Amplifier Design,”
*Proceedings*, IEEE International Symp. on Circuits and Systems, London, UK, May 30-June 2, 1994, pp. 93-96.
- Goes, J., Franca, J., Paulino, N., Grilo, J., and Temes, G.C., “High-Linearity Calibration of Low-Resolution D/A Converters,”
*Proceedings*, IEEE International Symp. on Circuits and Systems, London, UK, May 30-June 2, 1994, pp. 345-348.
- Hairapetian, A. and Temes, G.C., “A Dual-Quantization Multi-Bit Sigma-Delta A/D Converter,”
*Proceedings*, IEEE International Symp. on Circuits and Systems, London, UK, May 30-June 2, 1994, pp. 437-440.
- Yoshizawa, H. and Temes, G.C., “High-Linearity Switched-Capacitor Circuits in Digital CMOS Technology,”
*Proceedings*, IEEE International Symp. on Circuits and Systems, Seattle, WA, April 30-May 3, 1995, pp. 1029-1032.
- Cao, Y. and Temes, G.C., “CMOS Circuits for On-Chip Capacitance Ratio Testing on Sensor Readout,”
*Proceedings*, IEEE International Symp. on Circuits and Systems, Seattle, WA, April 30-May 3, 1995, pp. 1848-1851.
- Grilo, J., McRobbie, E., Halim, R., and Temes, G.C., “A 1.8 V 94 dB Dynamic Range Delta-Sigma Modulator for Voice Applications,”
*Digest*, IEEE International Solid-State Circuits Conference, San Francisco, CA, February 8-10, 1996, pp. 230-231 and 451.
- Huang, Y., Temes, G.C., and Ferguson, P., “Novel High-Frequency T/H Stages with Offset and Gain Compensation,”
*Proceedings*, IEEE International Symposium on Circuits and Systems, Atlanta, GA, May 12-15, 1996, pp. 155-158.
- Huang, Y., Temes, G.C., and Ferguson, P., “Reduced Nonlinear Distortion in Circuits with Correlated Double Sampling,”
*Proceedings*, IEEE International Symposium on Circuits and Systems, Atlanta, GA, May 12-15, 1996, pp. 159-162.
- Cauwenberghs, G. and Temes, G.C., “Adaptive Calibration of Multibit Quantization Oversampled A/D Converters,”
*Proceedings*, IEEE International Symposium on Circuits and Systems, Atlanta, GA, May 12-15, 1996, pp. 512-515.
- Wang, B., Sun, T., Cao, Y., and Temes, G.C., “High-Accuracy Circuits for On-Chip Capacitive Ratio Testing and Sensor Readout,”
*Proceedings*, IEEE International Workshop on Emergent Technologies for Instrumentation and Measurements, Como, Italy, June 10-11, 1996, pp. 68-75.
- Yoshizawa, H., Temes, G.C., Ferguson, P., and Krummenacher, F., “Novel Design Techniques for High-Linearity MOSFET-Only SC Circuits,”
*Digest*, 1996 Symposium on VLSI Circuits, Honolulu, HI, June 13-15, 1996, pp. 152-153.
- Wiesbauer, A. and Temes, G.C., “On-Line Digital Compensation of Analog Circuit Imperfections for Cascaded Delta-Sigma Modulators,”
*IEEE-CAS Workshop on Analog and Mixed IC Design*, Pavia, Italy, September 13-14, 1996, pp. 92-97.
- Wiesbauer, A. and Temes, G.C., “Adaptive Compensation of Analog Circuit Imperfections for Cascaded Delta-Sigma Modulators,”
*Asilomar Conference on Signals, Systems and Computers*, Pacific Grove, CA, November 3-6, 1996.
- Temes, G.C., “An Overview of Nyquist-Rate and Oversampled Data Converters in Telecommunications,” Keynote Address, Actas I.
*Conferencia Nacional de Telecomunicacoes*, Aveiro, Portugal, April 10-11, 1997, pp. 15-18.
- Huang, Y., Temes, G.C., and Yoshizawa, H., “A High-Linearity Low-Voltage All-MOSFET Delta-Sigma Modulator,”
*Proceedings*, IEEE Custom Integrated Circuits Conf., Santa Clara, CA, May 5-8, 1997, pp. 293-296.
- Wang, Bo, Kajita, T., Sun, T., and Temes, G.C., “High-Accuracy Circuits for On-Chip Capacitive Ratio Testing and Sensor Readout,”
*Proceedings*, IEEE Instrumentation and Measurement Techn. Conf., Ottawa, Canada, May 19-21, 1997, pp. 1169-1172.
- Yoshizawa, H., Huang, Y., and Temes, G.C., “MOSFET-Only Switched-Capacitor Circuits in Digital CMOS Technologies,”
*Proceedings*, IEEE Internat. Symp. on Circuits and Systems, Hong Kong, June 9-12, 1997, pp. 457-460.
- Grilo, J., Huang, Y., and Temes, G.C., “The Realization of Delta-Sigma A/D Converters in Low-Voltage Digital CMOS Technology,”
*Proceedings*, IEEE Midwest Symp. on Circuits and Systems, August 3-6, 1997.
- Kovacs, J. and Temes, G.C., “Analog CMOS ICs in Communication and Mass Storage Applications,”
*European Conf. on Circuit Theory and Design*, Budapest, Hungary, August 31-September 3, 1997.
- Huang, Y., Temes, G.C., and Ferguson, P., “Experimental Results on Reduced Harmonic Distortion in Circuits with Correlated Double Sampling,”
*Digest*, 1998 IEEE Symp. on VLSI Circuits, Honolulu, HI, June 9-11, 1998, pp. 224-227.
- Sun, T., Wiesbauer, A., and Temes, G.C., “Adaptive Compensation of Analog Circuit Imperfections for Cascaded Delta-Sigma ADCs,”
*Proceedings*, 1998 IEEE International Symp. on Circuits and Systems, Vol. I, Monterey, CA, May 31-June 3, 1998, pp. 405-407.
- Wang, B., Kajita, T., Sun, T., and Temes, G.C., “New High-Precision Circuits for On-Chip Capacitor Ratio Testing and Sensor Readout,”
*Proceedings*, 1998 IEEE International. Symp. on Circuits and Systems, Vol. I, Monterey, CA, May 31-June 3, 1998, pp. 547-550.
- Grilo, J.A. and Temes, G.C., “Predictive Correlated Double Sampling Switched-Capacitor Integrators,”
*Proceedings*, 1998 IEEE International Conf. on Electronics, Circuits and Systems, Lisboa, Portugal, September 7-10, 1998, pp. 2.9-2.12.
- Huang, Y., Temes, G.C., and Ferguson, P., “Offset- and Gain-Compensated Track-and-Hold Stages,”
*Proceedings*, 1998 IEEE International Conf. on Electronics, Circuits and Systems, Lisboa, Portugal, September 7-10, 1998, pp. 2.13-2.16.
- Grilo, J. and Temes, G.C., “The Use of Predictive Correlated Double Sampling Techniques in Low-Voltage Delta-Sigma Modulators,”
*Proceedings*, 1998 IEEE International Conf. on Electronics, Circuits and Systems, Lisboa, Portugal, September 7-10, 1998, pp. 2.149-2.152.
- Temes, G.C., “Oversampling A/D and D/A Converters,” invited paper, IX European Signal Processing Conf., Rhodes, Greece, September 8-11, 1998.
- Sun, T., Wiesbauer, A., and Temes, G.C., “Adaptive Compensation of Analog Circuit Imperfections for Cascaded Delta-Sigma ADCs,”
*Proceedings*, 24th European Solid-State Circuits Conf., The Hague, Netherlands, September 22-24, 1998.
- Temes, G.C., “Delta-Sigma Data Converters: The State-of-the-Art and Future Trends,” invited presentation,
*Proceedings*, NASA Symp. on VLSI Design, Albuquerque, NM, October 1-2, 1998, p. 6.1.
- Temes, G.C., “High-Linearity Switched-Capacitor Circuits Using MOSFET Gate-Channel Capacitors,” invited plenary lecture,
*Proceedings*, XIII Design of Circuits and Integrated Systems Conf., Madrid, Spain, Nov. 17-20, 1998, pp. X-XI.
- Steensgaard, J., Moon, U. and Temes, G.C., “Mismatch-Shaped Pseudo-Passive Two-Capacitor DAC,”
*Proceedings*, IEEE Alessandro Volta Workshop on Low-Voltage Design, Como, Italy, March 4-5, 1999, pp. 144-152.
- Steensgaard, J., Moon, U., and Temes, G.C., “Mismatch-Shaping Serial Digital-to-Analog Converter,”
*Proceedings*, IEEE Int. Symp. Circuits and Systems, vol. II, May 30-June 2, 1999, pp. 5-8.
- Bidari, E., Keskin, M., Maloberti, F., Moon, U., Steensgaard, J., and Temes, G., “Low-Voltage Switched-Capacitor Circuits,”
*Proceedings*, IEEE Int. Symp. Circuits and Syst., vol. II, May 30-June 2, 1999, pp. 49-52.
- Zheng, Z., Moon, U., Steensgaard, J., Wang, B., and Temes, G., “Capacitor Mismatch Error Cancellation Technique for a Successive-Approximation A/D Converter,”
*Proceedings*, IEEE Int. Symp. Circuits and Syst., vol. II, May 30-June 2, 1999, pp. 326-329.
- Temes, G.C., “Accurate Linear Analog Signal Processing and Data Conversion Using Inaccurate Nonlinear Components,” Keynote address, 42nd IEEE Midwest Circuit Symp., Las Cruces, NM, August 8-11, 1999.
- Wang, B. and Temes, G.C., “Novel CMFB Circuits for Stages with Large Common-Mode Input,”
*Proceedings*, European Conf. on Circuit Theory and Design, Stresa, Italy, vol. I, August 29-September 2, 1999, pp. 9-12.
- Temes, G., Moon, U., and Steensgaard, J., “Analog (S)witchcraft, or How to Perform Accurate and Linear Data Conversion Using Inaccurate Nonlinear Elements,” Plenary lecture, IEEE Elec. Circuits Syst. Conf., Bratislava, Slovakia, September 6-8, 1999, pp. 97-101.
- Moon, U., Temes, G., Bidari, E., Keskin, M., Wu, L., Steensgaard, J., and Maloberti, F., “Switched-Capacitor Circuit Techniques in Submicron Low-Voltage CMOS,” IEEE Int. Conf. VLSI CAD, Seoul, Korea, October 1999, pp. 349-358.
- Ferguson, P., Haurie, X. and Temes, G.C., “A Highly Linear Low-Power 10-Bit DAC for GSM,”
*Proceedings*, IEEE Custom Integrated Circuits Conf., Orlando, FL, May 21-24, 2000.
- Zheng, Z., Min, B., Moon, U., and Temes, G., “Efficient Error-Cancelling Algorithmic ADC,”
*Proceedings*, IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 28-31, 2000.
- Kiss, P., Silva, J., Moon, U., Stonick, J., and Temes, G., “Improved Adaptive Digital Compensation for Cascaded Delta-Sigma ADCs,”
*Proceedings*, IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 28-31, 2000, pp. 33-36.
- Kajita, T., Moon, U., and Temes, G., “A Noise-Shaping Accelerometer Interface Circuit for Two-Chip Implementation,”
*Proceedings*, IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 28-31, 2000, pp. 337-340.
- Moon, U., Silva, J., Steensgaard, J., and Temes, G., “A Switched-Capacitor DAC with Analog Mismatch Correction,”
*Proceedings*, IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 28-31, 2000, pp. 421-424.
- Wu, L., Keskin, M., Moon, U., and Temes, G., “Efficient Common-Mode Feedback Circuits for Pseudo-Differential Switched-Capacitor Stages,”
*Proceedings*, IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 28-31, 2000, pp. 445-448.
- Keskin, M., Moon, U., and Temes, G., “Low-Voltage Switched-Capacitor Resonators,” IEEE Dallas Workshop Low Power/Voltage Circuits Syst., March 2001, pp. 19-22.
- Kajita, T., Moon, U., and Temes, G., “A Noise-Shaping Accelerometer Interface Circuit for Two-Chip Implementation,”
*Proceedings*, IEEE Inst. Meas. Technology Conf., BudapestHungary, May 2001, pp. 1581-1586.
- Kiss, P., Moon, U., Steensgaard, J., Stonick, J., and Temes, G., “Multibit DS ADC with Mixed-Mode DAC Error Correction,”
*Proceedings*, IEEE Int. Symp. Circuits Syst., May 2001, pp. 280-283.
- Keskin, M., Moon, U., and Temes, G., “Low-Voltage Low-Sensitivity Switched-Capacitor Bandpass DS Modulator,”
*Proceedings*, IEEE Int. Symp. Circuits Syst., May 2001, pp. 348-351.
- Perigny, R., Moon, U., and Temes, G., “Area Efficient CMOS Charge Pump Circuits,”
*Proceedings*, IEEE Int. Symp. Circuits Syst., May 2001, pp. 492-495.
- Keskin, M., Moon, U., and Temes, G., “A 1-V, 10 MHz Clock Rate, 13-Bit ΔΣ Modulator Using Unity-Gain-Reset Op Amps,”
*Proceedings*, European Solid-State Circuits Conf., Villach, Austria, September 2001, pp. 532-535.
- Silva, J., Wang, X., Kiss, P., Moon, U., and Temes, G.C., “Digital Techniques for Improved Delta-Sigma Data Conversion,” Invited Paper,
*Proceedings*, IEEE Custom Integrated Circuits Conf., May 2002, pp. 183-186.
- Wang, X., Moon, U., Liu, M., and Temes, G.C., “Digital Correlation Technique for the Estimation and Correction of DAC Errors in Multibit MASH Delta-Sigma ADCs,”
*Proceedings*, IEEE Int. Symp. Circuits Syst., Phoenix, AZ, May 2002, vol. IV, pp. 691-694.
- Rao, A., McIntyre, W., Parry, J., Moon, U., and Temes, G.C., “Buck-BoostSC DC-DC Voltage Regulator Using Delta-Sigma Control Loop,”
*Proceedings*, IEEE Int. Symp. Circuits Syst., Phoenix, AZ, May 2002, vol. IV, pp. 743-746.
- X. Wang, Kiss, P., Moon, U., and Temes, G.C., “Digital Correlation Technique for the Estimation and Correction of DAC Errors in Multibit MASH Delta-Sigma ADCs,”
*Proceedings*, Int. Conf. on Advanced A/D & D/A Techn., Prague, Czech Rep., June 2002.
- M. Keskin, M. Brown, Moon, U., and Temes, G.C., “A Voltage-Mode SC Bandpass Delta-Sigma Modulator,”
*Proceedings*, Int. Conf. on Advanced A/D & D/A Techn., Prague, Czech Rep., June 2002.
- Markus, J. and Temes, G.C., “An Efficient Sigma-Delta Noise-Shaping Architecture for Wide-Band Applications,”
*Proceedings*, Int. Conf. on Advanced A/D & D/A Techn., Prague, Czech Rep., June 2002.
- Rao, A., McIntyre, W., Moon, U., and Temes, G.C., “A Noise-shaped SC DC-DC Voltage Regulator,”
*Proceedings*, ESSCIRC Dig. Tech. Papers, Florence, Italy, September 22-24, 2002, pp. 375-378.
- Bruneau, D., Early, A., Moon, U., and Temes, G.C., “High-Speed Switched-Capacitor Filters Based on the Unity-Gain Buffer,” IEEJ Analog VLSI Workshop, September 2002, pp. 5-9.
- Keskin, M., Moon, U., and Temes, G.C., “A 0.9-V 10.7-MHz 3.6 mW Bandpass ΔΣ Modulator Using Unity-Gain-Reset Opamps,”
*Proceedings*, IEEE Int. Workshop ADC Mod. Test., September 2003.
- Keskin, M., Moon, U., and Temes, C., “Amplifier Imperfection Effects in Switched-Capacitor Resonators,”
*Proceedings*, IEEE Int. Workshop ADC Mod. Test., September 2003.
- Markus, J., Silva, J., and Temes, G.C., “Design Theory for High-Order Incremental Converters,”
*Proceedings*, IEEE Internat. Symp. on Intelligent Signal Processing (WISP/2003), Budapest, Hungary, September 2003.
- Dai, S., von Jouanne, A., Wallace A., and Temes, G.C., “Delta-Sigma Modulation Applications in Neutral-Point Clamped Inverters,”
*Proceedings*, IAS2003, Salt Lake City, October 2003.
- Ceballos, J. and Temes, G.C., “Some Techniques to Improve the Performance of Delta-Sigma Modulators,” X. IBERCHIP Workshop, Cartagena de Indias, Columbia, March 10-12 2004.
- Xiao, Y., Moon, U. and Temes, G., "A Tunable Duty-Cycle-Controlled Switched-R-MOSFET-C Filter for Low-Voltage and High-Linearity Applications," Proc. IEEE Internat. Symp. on Circuits and Systems, Vancouver, Canada, vol. I, pp. 433-436, May 23-26, 2004.
- Silva, J., Moon, U. and Temes, G., "Low-Distortion Delta-Sigma Topologies for MASH Architectures," Proc. IEEE Internat. Symp. on Circuits and Systems, Vancouver, Canada, vol. I, pp.1144-1147, May 23-26, 2004.
- Ceballos, J. Steensgaard, J. and Temes, G., "A Digital Correction Scheme for Multibit Delta-Sigma D/A Converters," 11th Electronic Devices and Systems Conference, Czech Republic, Sept. 9 -10, 2004.
- Wang, X., Guo, Y., Moon, U. and Temes, G., "Experimental Verification of a Correlation-Based Correction Algorithm for Multi-Bit Delta-Sigma ADCs," IEEE Custom Integrated Circuits Conf., pp. 523-526, Oct. 2004.
- Han, J., von Jouanne, A. and Temes, G., "A New Approach to Reducing Output Ripple in Switched-Capacitor-Based Step-Down DC/DC Converters," IEEE IAS 39th Annual Meeting, Oct. 2004, Vol. 2, pp.1115-1120.
- Ahn, G., Chang, D., Brown, M., Ozaki, N., Youra, H., Yamamura, K., Hamashita, K., Temes, G. and Moon, U., "A 0.6 V 82 dB Delta-Sigma Audio ADC Using Switched-RC Integrators," IEEE Internat. Solid-State Circuits Conf. Digest, 48, Febr. 6-10, 2005, pp. 166-167.
- Han, J., von Jouanne, A. and Temes, G., "Design and IC Implementation of an Ultra-Low-Ripple Switched-Capacitor-Based Buck DC-DC Converter," Applied Power Electronics Conference and Exposition, March 6-10, 2005, Austin, TX, Vol. 3, pp.1447-1452.
- Ceballos, J. and Temes, G., "Improved Current Cells for Current-Steering Digital-to-Analog Converters," XI IBERCHIP WORKSHOP, March 2005, Salvador de Bahia-Brasil.
- Ceballos, J., Steensgaard, J. and Temes, G., "Digital Correction for Multibit D/A Converters,” XI IBERCHIP WORKSHOP, March 2005, Salvador de Bahia-Brasil.
- Rengachari, T., Sharma, V. Temes, G. and Moon, U., “A 10-Bit Algorithmic A/D Converter for Cytosensor Application," Proc. IEEE Internat. Symp. on Circuits and Sys., May 23-26, 2005, Kobe, Japan.
- Sharma, V., Moon, U. and Temes, G., “A Generic Multilevel Multiplying D/A Converter for Pipeline ADCs,” Proc. IEEE Internat. Symp. on Circuits and Sys., May 23-26, 2005, Kobe, Japan.
- Steensgaard, J., Zhang, Z. and Temes, G., “Dual-Path Delta-Sigma Modulators,” IEEE Int. Midwest Symp. on Circuits and Symp., Cincinnati, Aug. 7-10, 2005.
- Ceballos, J., Galton, I. and Temes, G., “Stochastic Analog-to-Digital Conversion,” IEEE Int. Midwest Symp. on Circuits and Symp., Cincinnati, Aug. 7-10, 2005.
- Quiquempoix, V., Deval, Ph., Barreto, A., Bellini, G., Collings, J., Markus, J., Silva, J. and Temes, G., “A Low-Power 22-Bit Incremental ADC with 4 ppm INL, 2 ppm Gain Error and 2 uV DC Offset,” IEEE European Solid-State Circuits Conference Sept. 12-16, 2005.
- Ahn G., P. Hanumolu, M. Kim, S. Takeuchi, T. Sugimoto, K. Hamashita,, Takeuchi, S., Temes, G.C. and Moon, U., “A 12b 10MS/s Pipelined ADC Using Reference Scaling,” IEEE Symp. on VLSI Circuits, pp. 220-221, June 2006.
- Kim, M.G., Ahn, G.C., Hanumolu, P.K., Lee, S., Kim, S., You, J., Temes, G. and Moon, U., “A 0.9V 92dB Double-Sampled Switched-RC Delta-Sigma Audio ADC,” IEEE Symp. on VLSI Circuits, pp. 160-161, June 2006.
- Meng, Q., Lee, K., Sugimoto, T., Hamashita, K., Takasuka, K., Takeuchi, S., Moon, U. and Temes, G., “A 0.8V, 88dB Dual-Channel Audio Delta-Sigma DAC with Headphone Driver,” IEEE Symp. on VLSI Circuits, pp. 53-54, June 2006.
- Yoshizawa, H. and Temes, G., “Switched-Capacitor Track-and-Hold Amplifier with Low Sensitivity to Op-Amp Imperfections,” Proc. IEEE Int. Symp. on Circuits and Sys., May 2006.
- Markus, J., Deval, Ph., Quiquempoix, V., Silva, J. and Temes, G., “Incremental Delta-Sigma Structures for DC Measurement: An Overview,” IEEE Custom IC Conf. 2006, Invited Paper, pp. 41-48, Sept. 2006.
- Kurahashi, P., Hanumolu, P., Temes, G. and Moon, U., “A 0.6V Highly Linear Switched-R-MOSFET-C Filter,” IEEE Custom IC Conf. 2006, Best Student Paper award, pp. 833-836, Sept. 2006.
- Lee, K. and Temes, G.C., “Enhanced Split-Architecture Delta-Sigma ADC,” Internat. Conf. on Electronics, Circuits and Systems, Nice, France, Dec. 10-13, 2006.
- Sharma, V. Moon, U. and Temes, G.C., “Efficient Pipelined ADCs Using Integer-Gain MDACs,” IEEE Conf. on PhD Research in Microelectronics, Bordeaux, France, July 2-5, 2007.
- Lee, K., Temes, G.C. and Maloberti, F., “Noise-Coupled Multi-Cell Delta-Sigma ADCs,” IEEE Internat. Symp. On Circuits and Systems, New Orleans, LA, pp. 249-252, May 27-30, 2007.
- Zhang, Zh. and Temes, G.C., “A Segmented Data-Weighted Averaging Technique,” IEEE Internat. Symp. On Circuits and Systems, New Orleans, LA, pp. 481-484, May 27-30, 2007.
- Yoshizawa, H. and Temes, G.C., “Predictive Switched-Capacitor Track-and Hold Amplifier with Improved Linearity,” IEEE Internat. Symp. On Circuits and Systems, New Orleans, LA, pp. 233-236, May 27-30, 2007.
- Maghari, N., Kwon, S., Temes, G.C. and Moon, U., “Mixed-Order Sturdy MASH Delta-Sigma Modulator,” IEEE Internat. Symp. On Circuits and Systems, New Orleans, LA, pp. 257-260, May 27-30, 2007.
- Zhang, Zh., Steensgaard, J., Temes, G.C. and Wu, J., “A Split 2-0 MASH with Dual Digital Error Correction,” IEEE Symp. on VLSI Circuits, Kyoto, Japan, pp. 242-243, June 14-16, 2007.
- Zhang, Zh., Yu, W., Lucchese, L. Kim, D. and Temes, G.C., “Multiplexed Incremental ADCs,” IEEE Midwest Symp. on Circuits and Systems, Montreal, Canada, Aug. 5-8, 2007.
- Chen, X., Wang, Y., Fujimoto, Y., Lo Re, P., Kanazawa, Y., Steensgaard, J. and Temes, G.C., “A 18mW CT DS Modulator with 25MHz Bandwidth for Next Generation Wireless Applications,” IEEE Custom IC Conf. Digest, pp. 73-76, Sept. 2007.
- Lee, K., Chae, J, Aniya, M., Hamashita, K., Takasuka, K., Takeuchi. S. and Temes, G.C., “A Noise-Coupled Time-Interleaved DS ADC with 4.2MHz, BW, -98dB THD and 79dB SNDR,”IEEE Internat. Solid-State Circuits Conf., pp. 12-14, Febr. 2008.
- Lee, K. and Temes, G.C., “Efficient Fully-Floating Double-Sampling Integrator for Delta-Sigma ADCs,” 2008 IEEE Internat. Symp. On Circuits and Systems, pp.1440-1443, May 2008.
- Wang, Y., Lee, K. and Temes, G.C., “A 2.5 MHz BW and 78 dB SNDR Delta-Sigma Modulator Using Dynamically Biased Amplifiers,” IEEE Custom IC Conf. Digest, pp. 97-100, Sept. 2008.
- Lee. K., Miller, M. and Temes, G.C., “An 8.1 mW, 82 dB Delta-Sigma ADC with 1.9 MHz BW and -98 dB THD,” IEEE Custom IC Conf. Digest, pp. 93-96, Sept. 2008.
- Temes, G.C., “New Architectures for Low-Power Delta-Sigma ADCs,” Keynote Address, IEEE Asia Pacific Conf. on Circuits and Systems, Dec. 2008.
- Nishida, Y. and Temes, G.C., “An Enhanced Dual-Path Delta-Sigma ADC,” 2009 IEEE Internat. Symp. on Circuits and Systems, pp. 1333-1336, May 2009.
- Yu, W. and Temes, G.C. “A Digital Calibration Technique for DAC Mismatches in Delta-Sigma Modulators,” 2009 IEEE Internat. Symp. on Circuits and Systems, pp. 1337-1340, May 2009.
- Lee, K. and Temes, G.C.,”Improved Low-Distortion Delta-Sigma ADC Topology,” 2009 IEEE Internat. Symp. on Circuits and Systems, pp. 1341-1344, May 2009.
- Shen, W. and Temes, G.C., “Double-Sampled Delta-Sigma Modulator with Relaxed Feedback Timing,” Midwest Symp. on Circuits and Systems, pp. 93-96, Aug. 2-5, 2009.
- Wang, Y. and Temes, G.C., “Delta-Sigma ADCs with Second-Order Noise Shaping Enhancement,” Midwest Symp. on Circuits and Systems, pp. 345-348, Aug. 2-5, 2009.
- Wang, Y. and Temes, G.C., “Noise-Coupled Continuous-Time Delta-Sigma ADCs,” Midwest Symp. on Circuits and Systems, pp. 341-344, Aug. 2-5, 2009.
- Wang, Y. and Temes, G.C., “Wideband Delta-Sigma ADCs Using Direct-Charge-Transfer Adder,” Midwest Symp. on Circuits and Systems, pp. 93-96, Aug. 2-5, 2009.
- Wang, Y. and Temes, G.C., “Low-Distortion Double-Sampling Delta-Sigma ADC Using a Direct-Charge-Transfer Adder,” IEEE SOOC Conf., pp. 71-74, Sept. 9-11, 2009.
- Lee, K. and Temes, G.C., “Noise-Coupled Delta-Sigma Data Converters,” AACD 2010, Graz, Austria, March 23-25, 2010.
- Cao, J. and Temes, G.C., “Radix-Based Digital Correction Technique for Two-Capacitor DACs,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 565-568, June 2010.
- Yu, W., Lin, j. and Temes, G.C., “Two-Step Junction-Splitting SAR Analog-to-Digital Converter,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 1448-1451, June 2010.
- Lin, J., Yu, W. and Temes, G.C., “Energy-Efficient Time-Interleaved and Pipelined SAR ADCs,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 1452-1455, June 2010.
- Wang, Y. and Temes, G.C., “Design Techniques for Discrete-Time Delta-Sigma ADCs with Extra Loop Delay,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 2159-2162, June 2010.
- Zanbaghi, R., Fiez, T. And Temes, G.C., “A New Zero-Optimization Scheme for Noise-Coupled Delta-Sigma ADCs,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 2163-2166, June 2010.
- Wang, T. and Temes, G.C., “Switched-Resistor Tuning Techniques for Higly Linear Gm-C Filter Design,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 3617-3620, June, 2010.
- Wang, Y., Chen, Ch., Yu, W. and Temes, G.C., “Noise-Coupled Low-Power Incremental ADCs,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 4001-4004, June, 2010.
- Wang, T. and Temes, G.C., “Low-Power Switched-Capacitor Integrator for Delta-Sigma ADCs,” Internat. Midwest Symp. on Circuits and Systems, pp. 493-496, Aug. 2010.
- Zanbaghi, R. and Temes, G.C., “An Op-Amp Sharing Technique for Continuous-Time Delta-Sigma Modulators,” IEEE Internat. Midwest Symp. on Circuits and Systems, pp. 592-595, Aug. 2010.
- Shen, W., Wang, T. and Temes, G.C., “Low-Distortion Delta-Sigma Modulator Employing Modified Charge-Pump Based Switched-Capacitor Integrator,” IEEE Internat. Midwest Symp. on Circuits and Systems, pp. 901-904, Aug. 2010.
- Yu, W., Aslan, M. and Temes, G.C., “82-dB SNDR 20-Channel Incremental ADC with Optimal Decimation Filter and Digital Correction,” IEEE Custom Integrated Circuits Conf., pp. 1-4, Sept. 21, 2010.
- Chae, J., Lee, S., Anija, M., Takeuchi, S., Hamashita, K. Hanumolu, P. and Temes, G.C., “A 63 dB, 16 mW, 20 MHz BW Double-Sampled ADC with an Embedded-Adder Quantizer,” IEEE Custom Integrated Circuits Conf., pp. 1-4, Sept. 21, 2010.
- Lee, S. et al, “A Double-Sampled Low-Distortion Cascade ΔΣ Modulator with an Adder/Integrator for WLAN Application,” IEEE Custom Integrated Circuits Conf., San Jose, CA, Sept. 18 – 21, 2011.
- Zanbaghi, R., Saxena, S., Temes, G.C. and Fiez, T.S., “A 75 dB SNDR, 10 MHz Conversion Bandwidth Stage-Shared 2-2 Mash ΔΣ Modulator Dissipating 9 mW,” IEEE Custom Integrated Circuits Conf., San Jose, CA, Sept. 18 – 21, 2011.
- Li, Wei and Temes, G.C., “Digital Foreground Calibration Methods for SAR ADCs,” IEEE Internat. Circuits and Systems Symp., pp. 1054-1057, May 20-23, 2012, Seoul, Korea.
- Chen, C.H., Crop, J., Chae, J., Chiang, P. and Temes, G.C., “A 12-Bit, 7 uW/Channel, 1 kHz/Channel Incremental ADC for Biosensor Interface Circuits,” IEEE Internat. Circuits and Systems Symp., May 20-23, 2012, pp. 2969 – 2972, Seoul, Korea.
- Cao, J., Raich, R., Cauwenberghs, G. and Temes, G.C., “Multi-Channel Mixed-Signal Noise Source with Applications to Stochastic Equalization,” IEEE Internat. Circuits and Systems Symp., pp. 2497-2500, May 20-23, 2012, Seoul, Korea.
- Tong, T. and Temes, G.C., “Calibration Technique for SAR Analog-to-Digital Converters,” IEEE Internat. Circuits and Systems Symp., pp. 2993-2996, May 20-23, 2012, Seoul, Korea
- Wang, T., Li, W., Yoshizawa, H., Aslan, M. and Temes, G.C., “A 101-dB DR 1.1-mW Audio ΔΣ Modulator with Direct-Charge-Transfer Adder and Noise Shaping Enhancement,” IEEE Asian Solid-State Circuits Conf., Nov. 12-14, 2012, Kobe, Japan.
- Meng, X., Temes, G.C. and Wang, T., “A Low-Power Parasitic-Insensitive Switched-Capacitor Integrator for ΔΣ ADCs,” IEEE Internat. Circuits and Systems Symp., June 1 – 5, 2014, Melbourne, Australia.
- Meng, X., Li, W. and Temes, G.C. “A Fully Differential Input Amplifier With Bandpass Filter for Biosensors,” IEEE Internat. Circuits and Systems Symp., June 1 – 5, 2014, Melbourne, Australia.
- Zhang, Y., Chen, Ch., He, T. and Temes, G.C., “A Continuous-Time ΔΣ Modulator with a Digtal Technique for Excess Loop Delay Compensation,” IEEE Internat. Circuits and Systems Symp., June 1 – 5, 2014, Melbourne, Australia.
- Meng, X. and Temes, G.C., “Bootstrapping techniques for floating switches in switched-capacitor circuits,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 3-6, 2014, College Station, TX
- Meng, X. and Temes, G.C., “Low-power duty-cycle tuned filters,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 3-6, 2014, College Station, TX.
- Meng, X. and Temes, G.C., “A noise-coupled low-distortion delta-sigma ADC with shifted loop delays,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 3-6, 2014, College Station, TX.
- Meng, X. and Temes, G.C., “Double-sampled wideband delta-sigma ADC with shifted loop delays,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 3-6, 2014, College Station, TX.
- Payandehnia, P. et al., “Sequential interstage correlated double sampling,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 3-6, 2014, College Station, TX.
- Payandehnia, P. et al., “Multistep counting ADC,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 3-6, 2014, College Station, TX.
- Li, W., WangT., Grilo, J.A., and Temes,G.C. “A 0.45mW 12b 12.5MS/s SAR ADC with digital calibration,” IEEE Custom Integrated Circuits Conf., San Jose, CA, Sept. 15 – 17, 2014.
- Chen, C-H, Zhang, Y., He, T., Chiang, P.Y. and Temes, G.C., “A 11µW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces,” IEEE Custom Integrated Circuits Conf., San Jose, CA, Sept. 15 – 17, 2014.
- Zhang, Y., Chen, C-H, He, T. and Temes, G.C., “A 1 V, 59 fJ/Step, 15 MHz BW, 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback,” IEEE Asian Solid-State Circuits Conference, KaoHsiung, Taiwan, Nov. 10-12, 2014.
- Chen, C-H, He, T. and Temes, G.C., “Micro-power incremental ADCs,” Proc. Advances in Analog Circuit Design (AACD) Workshop,
*invited*, Neuchatel, Switzerland, April 21-23, 2015, pp. 1- 19.
- Payandehnia, P., Fazli, A., Meng, X., Yang, Chao and Temes, G.C., “A passive CMOs low-pass filter for high speed and high SNDR applications,” IEEE Internat. Circuits and Systems Symp., May 24 - 27, 2015, Lisbon, Portugal.
- He, T. Tao He, Yi Zhang, Xin Meng and Gabor Temes and Chia-hung Chen, “Micro-Power Multi-Step Incremental ADCs for Multi-Channel Sensor Interfaces,” IEEE Internat. Circuits and Systems Symp., May 24 - 27, 2015, Lisbon, Portugal.
- Sadollahi,M. and Temes, G., “Two-stage ΔΣ ADC with noise-coupled VCO-based quantizer,” IEEE Internat. Circuits and Systems Symp., May 24 - 27, 2015, Lisbon, Portugal.
- Meng, X., Zhang, Y., He, T., Payandehnia, P. and Temes, G.C., “A noise-coupled time interleaved ΔΣ modulator with shifted group delay,” IEEE Internat. Circuits and Systems Symp., May 24 - 27, 2015, Lisbon, Portugal.
- Meng, X. et al.,"A 19.2-mW, 81.6-dB SNDR, 4-MHz Bandwidth Delta-Sigma Modulator with Shifted Loop Delays," IEEE European Solid-State Device Research & Circuits Conference, September 14-18, 2015, Graz, Austria.
- Vahid Behravan, Shuo Li, Neil E. Glover, Chia-Hung Chen, Mohammed Shoaib, Gabor C. Temes and Patrick Y. Chiang, “A Compressed-Sensing Sensor-on-Chip Incorporating Statistics Collection to Improve Reconstruction Performance,” IEEE Custom Integrated Circuits, Conf., San Jose, CA, Sept. 18 – 21, 2015.
- C.–H. Chen, Y. Zhang, T. He, and G. C. Temes, “An incremental analog-to-digital converter with multi-step extended counting for sensor interfaces,”
*IEEE Internat. Circuits and Systems Symp*, 2016, Montreal, Canada, pp. 77 – 80.
- J. Cao and G. C. Temes, “Power-on Digital Calibration Method for Delta-Sigma ADCs,”
*IEEE International Circuits and Systems Symp*, 2016, pp.2002-2005.
- Zhang, Y., C-H Chen, He, T. and G.C. Temes, “A 35 uW 96.8 dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator,”
*IEEE 2016 Symp. on VLSI Circuits, *Honolulu, pp. 1-2.
- Chia-Hung Chen, Yi Zhang, Gabor C. Temes, “History, present state-of-art and future of incremental ADCs,” ESSCIRC European Solid-State Circuits Conference, 2016, pp. 83–86.
- Zhang, Y.,C-H Chen, He, T. and G.C. Temes, “A two-capacitor SAR-assisted multi-step incremental ADC with a single-amplifier achieving 96.6 dB SNDR over 1.2 kHz BW,” IEEE Custom Integrated Circuits Conf., Austin, TX, Apr. 30 – May 3, 2017.
- He, T., Chen, C-H., Zhang, Y. and Temes, G.C., “Incremental ADC with Parallel Counting,” IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, August 6-9, 2017.
- Sadollahi, M., Hamashita, K. Sobue, K. and Temes, G.C., “An 11-bit 250 nW 10 kS/s SAR ADC with doubled input range for biomedical applications,” IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, August 6-9, 2017.
- Sadollahi, M., Hamashita, K. Sobue, K. and Temes, G.C., “Passive 3
^{rd}-order delts-sigma ADC with VCO-based quantizer,” IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, August 6-9, 2017.
- He, T., Kareppagoudr, M., Zhang, Y., Moon, U. and Temes, G.C., “Pseudo-pseudo differential circuits," IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, August 6-9, 2017.

#### Book Review

- Temes, G.C., Review of “Signals, Systems, and Networks,” by G. Fodor, IEEE Circuits and Systems Magazine, July 2003.

#### PATENTS

- “D.C. Bias Servomethod and Apparatus for Magnetic Recording Heads,” (with P. Bajka), U.S. Patent 3,564,160, February 1971.
- “Variable Sample Periodic Hold Electronic Delay Network,” U.S. Patent 3,587,007, June 1971.
- “Asymmetrical Loss-Pole Mechanical Filter,” U.S. Patent 3,725,828, April 1973.
- “Photo Detector Input Circuit,” U.S. Patent 4,173,723, November 11, 1979.
- “Offset Compensated Switched-Capacitor Circuits,” U.S. Patent 4,543,534, September 1985.
- “Pixel Non-Uniformity Correction System,” U.S. Patent, 4,602,291, July 1986.
- “Aktives Netzwerk,” West German Patent DE3401516C2, October 1986.
- “Switched-Capacitor Pseudo-N-Path Filter,” U.S. Patent 4,644,304, February 1987.
- “Pipelined Digital-to-Analog Converter,” U.S. Patent 4,713,650, December 1987.
- “Multi-Stage Sigma-Delta Analog-to-Digital Converter,” U.S. Patent 5,153,593, October 6, 1992.
- “High-Order Sigma-Delta Analog-to-Digital Converter,” U.S. Patent 5,198,817, March 30, 1993.
- “Dual-Quantization Oversampling Digital-to-Analog Converter,” U.S. Patent 5,369,403, November 29, 1994.
- “Track-and-Hold Circuit Utilizing a Negative of the Input Signal for Tracking,” U.S. Patent 5,689,201, November 18, 1997.
- “Method and Apparatus for Use in Switched-Capacitor Circuits,” U.S. Patent 6,873,278, March 29, 2005; European Patent Application, May 21, 2001.
- “Switched-Capacitor Signal Scaling Circuit” U.S. Patent 7,046,046, Oct. 13, 2005.

Rev. 7/2017