Research Areas
Error Control Codes, VLSI Testing, Parallel Processing, Fault Tolerant Computing

Research Description
My current research interests are in error control codes, VLSI testing, parallel processing, and fault tolerant computing.

We are developing efficient codes for unidirectional/asymmetric errors in the area of error control coding. Simple and efficient design of encoder/decoder algorithms are also being studied. Further, we have been developing efficient design methods for balanced codes, where each codeword contains equal number of 1's and 0's.

In the area of VLSI testing, we are investigating new and efficient methods for compression testing. Our research also involves the application of these schemes for built-in-self-testing in VLSI systems. Efficient design of communications algorithms, mapping algorithms, etc., with or without some faulty nodes in different networks are some of the parallel processing research problems that we are currently investigating. Furthermore, using coding theory, some topological properties of different networks are being developed

Recent Research Collaborations & Projects

• National Science Foundation: "Some Coding Techniques for VLSI and Computer Systems," September 2001-August 2004, $300,319
• National Science Foundation: "Some Coding Techniques for VLSI Systems," September 1997-August 2002, $407,105
• American Bureau of Shipping: "Development of Integration Techniques for Engineering Analysis," September 2001-August 2002, $9,529