Self-Healing RF Circuits

• Yike Cui, Baoyong Chi, Minjie Liu, Yulei Zhang, Yongming Li, Patrick Chiang, Zhihua Wang. Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance. Submitted to International Symposium on Circuits and Systems, 2007.

Thesis Work

• Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer. IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, April 2005, pp. 1004-1011.
• Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer. 2004 Symposium on VLSI Circuits, June 15-19, 2004, pp. 272-275.
• Patrick Chiang, William J. Dally, Ming-Ju E. Lee. A 20Gb/s 0.13um CMOS Serial Link, Hotchips 2002, Stanford, CA, Aug. 18-20, 2002.

Nonlinear Chaotic Communcations Transceiver

• Patrick Chiang, William J. Dally, Ming-Ju E. Lee. Monolithic Chaotic Communications System. 2001 IEEE International Conference on Circuits and Systems, Sydney, Australia, May 6-9, 2001.

Low Power, Area Efficient Serial Link

• Ming-Ju E. Lee, William J. Dally, John W. Poulton, Patrick Chiang, Stephen F. Greenwood. An 84-mW 4Gb/s Clock and Data Recovery Circuit for Serial Link Applications. VLSI Circuits Symposium, Kyoto, Japan, June 2001, pp. 149-152.
• Ming-Ju E. Lee, William Dally, Patrick Chiang. Low-Power Area-Efficient High-Speed I/O Circuit Techniques. IEEE Journal of Solid-State Circuits, November 2000, Vol. 35, No. 11, pp. 1591-1599.
• Ming-Ju E. Lee, William Dally, Patrick Chiang. A 90mW 4Gb/s Equalized I/O Circuit with Input Offset Cancellation. International Solid State Circuits Conference, San Francisco, February 2000, TP 15.3, pp. 252-253.

Analog Front-End for DMT xDSL

• Cormac Conroy, Samuel Sheng, Arnold Feldman, Greg Uehara, Albert Yeung, Chih-Jen Hung, Vivek Subramanian, Patrick Chiang, Paul Lai, Xiaomin Si, Jerry Fan, David Flynn, Meiqing He. A CMOS Analog Front-End IC for DMT ADSL. International Solid State Circuits Conference, San Francisco, February 1999, pp. 240-241.

In Preparation

• T. Lamers, P. Chiang, R. Flynn, Y.R. Rau, K. Ioakeimidi, S. Devasenathipathy, B. Chui, B.L. Pruitt. An Electrically Addressable, Liquid Release Well Array for a Hand-held Scented Material Dispense System. In Submission to Hilton Head MEMS Conference 2006.
• Patrick Chiang, William J. Dally, Ming-Ju Edward Lee. A 20Mb/s Ultra-Wideband Transceiver in 0.25um CMOS Using Chaotic Pulse Position Modulation. In preparation.
• Patrick Chiang. Precision Clock Synthesis Using Direct Modulation of Front-End Multiplexers/Demultiplexers in High Speed Serial Links. Doctoral Thesis, 2006.