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Terri S. Fiez
Publications
Journal Papers
- U. Chilakapati and T.S. Fiez, "Effect of Switch Resistance on the SC Integrator Settling Time," IEEE Trans. Circuits & Systems, In Print.
- R. Naiknaware and T.S. Fiez, "Automated Hierarchical CMOS Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations," IEEE J. Solid-State Circuits, Vol. 34, no. 3, pp. 304-317, March 1999.
- E.T. King, A, Eshraghi, I. Galton, and T.S. Fiez, "A Nyquist Rate Delta-Sigma A/D Converter," IEEE J. Solid-state Circuits, vol. 33 no. 1 pp. 45-52, Jan. 1998.
Conference Proceedings
- A. Samavedam, K. Mayaram, and T.S. Fiez, "A Scalable Substrate Noise Coupling Model for Mixed-Signal ICs," ICCAD, Nov. 1999.
- A. Samavedam, K. Mayaram, and T.S. Fiez, "Design Oriented Substrate Noise Coupling Macromodels for Heavily Doped CMOS Processes," IEEE Intl. Sump. Circuits & Syst., May 1999.
- R. Naiknaware and T.S. Fiez, "Time Referenced Single-Path Multi-Bit Delta-Sigma ADC Using a VCO Based Quantizer," IEEE Intl. Symp. on Circuits & Syst., May 1999.
- R. Naiknaware and T.S. Fiez, "Switched-Capacitor Integrator Design Optimizing for Power and Process Variations," IEEE Intl. Symp on Circuits & Syst., May 1999.
- R. Radke, A. Eshraghi, and T.S. Fiez, "A Spurious-Free Delta-Sigma DAC Using Rotated Data Weighted Averaging," IEEE Custom Integrated Circuits Conf., May 1999.
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