Journal Papers

• D. Chang, J. Li, and U. Moon, "Radix-Based Digital Calibration Techniques for Multi-Stage Recycling Pipelined ADCs," IEEE Trans. Circuits Syst. I, accepted, 2004.
• P. Hanumolu, M. Brownlee, K. Mayaram, and U. Moon, "Analysis of charge-pump phased-locked loops," IEEE Trans. Circuits Syst. I, accepted, 2004.
• J. Li and U. Moon, "A 1.8V 67mW 10b 100MS/s Pipelined ADC using Timeshifted CDS Technique," IEEE J. Solid-State Circuits, accepted, 2004.
• S. Yoo, J. Park, S. Lee, and U. Moon, "A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching," IEEE Trans. Circuits Syst. II, vol. 51, no. 5, pp. 269-275, May 2004.
• C. Myers, B. Greenley, D. Thomas, and U. Moon, "Continuous-Time Filter Design Optimized for Reduced Die Area," IEEE Trans. Circuits Syst. II, vol. 51, no. 3, pp. 105-110, Mar. 2004.
• U. Moon and G. Huang, “CMOS Implementation of Nonlinear Spectral-Line Timing Recovery in Digital Data Communication Systems,” IEEE Trans. Circuits Syst. I, pp. 298-308, Feb. 2004.
• P. Hanumolu, B. Casper, R. Mooney, G. Wei, and U. Moon, "Analysis of PLL Clock Jitter in High-Speed Serial Links," IEEE Trans. Circuits Syst. II, pp. 879-886, Nov. 2003.
• J. Li and U. Moon, "Background Calibration Techniques for Multi-Stage Pipelined ADCs with Digital Redundancy," IEEE Trans. Circuits Syst. II, pp. 531-538, Sep. 2003.
• D. Chang and U. Moon, "A 1.4-V 10-bit 25MSPS Pipelined ADC Using Opamp-Reset Switching Technique," IEEE J. Solid-State Circuits, pp. 1401-1404, Aug. 2003.
• Y. Ou, N. Barton, R. Fetche, N. Seshan, T. Fiez, U. Moon, and K. Mayaram, "Phase Noise Simulation and Estimation Methods: A Comparative Study," IEEE Trans. Circuits Syst. II, pp. 635-638, Sep. 2002.
• T. Kajita, U. Moon, and G. Temes, "A Two-Chip Interface for a MEMS Accelerometer," IEEE Trans. Inst. Meas., vol. 51, no. 4, pp. 853-858, Aug. 2002.
• T. Kajita, U. Moon, and G. Temes, "A Noise-Shaping Accelerometer Interface Circuit for Two-Chip Implementation," VLSI Design, pp. 355-361, Jun. 2002.
• M. Keskin, U. Moon, and G. Temes, "A 1-V 10-MHz Clock-Rate, 13-bit CMOS ∆Σ Modulator using Unity-Gain-Reset Opamps," IEEE J. Solid-State Circuits, vol. 37, no. 7, pp. 817-824, Jul. 2002.
• M. Keskin, U. Moon, and G. Temes, "Direct-Charge-Transfer Pseudo-N-Path SC Circuit Insensitive to the Element Mismatch and Opamp Nonidealities," Analog Int. Circuits Sig. Proc., vol. 30, pp. 243-247, Mar. 2002.
• J. Silva, U. Moon, J. Steensgaard, and G. Temes, "A Wideband Low-distortion Delta-Sigma ADC Topology," Electron Lett., vol. 37, no. 12, pp. 737-738, Jun. 7, 2001.
• D. Chang and U. Moon, "1-V Input Sampling Circuit with Improved Linearity," Electron Lett., Vol. 37, no. 8, pp. 479-481, Apr. 8, 2001.
• X. Wang, P. Kiss, U. Moon, J. Steensgaard, and G. Temes, "Digital Estimation and Correction of DAC Errors in Multibit Delta-Sigma ADCs," Electron Lett., Vol. 37, no. 7, pp. 414-415, Mar. 29, 2001.
• M. Keskin, U. Moon, and G. Temes, "Switched-Capacitor Resonator Structure with Improved Performance," Electron Lett., vol. 37, no. 4, pp. 212-213, Feb. 15, 2001.
• T. Kajita, G. Temes, and U. Moon, "Correlated Double Sampling Integrator Insensitive to Parasitic Capacitance," Electron Lett., vol 37, no. 4, pp. 151-153, Feb. 1, 2001.
• P. Kiss, U. Moon, J. Steensgaard, J. Stonick, and G. Temes, "High-Speed Delta Sigma ADC with Error Correction," Electron Lett., vol. 37, no. 2, pp. 76-77, Jan. 18, 2001.
  

Conference Proceedings

• X. Wang, Y. Guo, U. Moon, and G. Temes, "Experimental Verification of a Correlation-Based Correction Algorithm for Multi-Bit Delta-Sigma ADCs," IEEE Custom Int. Circuits Conf., to appear, Oct. 2004.
• G. Vemulapalli, P. Hanumolu, and U. Moon, "A 0.8V Accurately-Tuned Continuous-Time Filter," IEEE Custom Int. Circuits Conf., to appear, Oct. 2004.
• C. Myers, J. Li, D. Chang, and U. Moon, "Low Voltage High-SNR Pipeline Data Converters," IEEE Northeast Workshop Circuits Syst., to appear, Jun. 2004.
• M. Brownlee, P. Hanumolu, U. Moon, and K. Mayaram, "The Effect of Power Supply Noise on Ring Oscillator Phase Noise," IEEE Northeast Workshop Circuits Syst., to appear, Jun. 2004.
• J. Li, G. Ahn, D. Chang, and U. Moon, "0.9V 12mW 2MSPS Algorithmic ADC with 81dB SFDR," IEEE Symp. VLSI Circuits, to appear, Jun. 2004.
• P. Hanumolu, B. Casper, R. Mooney, G. Wei, and U. Moon, "Jitter in Highspeed Serial and Parallel Links," IEEE Int. Symp. Circuits Syst., to appear, May 2004.
• S. Xiao, J. Silva, U. Moon, and G. Temes, "A Tunable Duty-Cycle-Controlled Switched-R-MOSFET-C CMOS Filter for Low-Voltage and High-Linearity Applications," IEEE Int. Symp. Circuits Syst., to appear, May 2004.
• J. Silva, U. Moon, and G. Temes, "Low-Distortion Delta-Sigma Topologies for MASH Architectures," IEEE Int. Symp. Circuits Syst., to appear, May 2004.
• M. Kim, G. Ahn, and U. Moon, "An Improved Algorithmic ADC Clocking Scheme," IEEE Int. Symp. Circuits Syst., to appear, May 2004.
• J. Li and U. Moon, "A 1.8-V 67mW 10-bit 100MSPS Pipelined ADC using Time-Shifted CDS Technique," IEEE Custom Int. Circuits Conf., pp. 413-416, Sep. 2003.
• B. Greenley, R. Veith, D. Chang, and U. Moon, "A 1.4V 10b CMOS DC DAC in 0.01mm^2," IEEE Int. SOC Conf., pp. 237-238, Sep. 2003.
• M. Keskin, U. Moon, and G. Temes, "Amplifier Imperfection Effects in Switched-Capacitor Resonators," IEEE Int. Workshop ADC Mod. Test., pp. 67-70, Sep. 2003.
• M. Keskin, U. Moon, and G. Temes, "A 0.9-V 10.7-MHz 3.6-mW Bandpass ∆Σ Modulator using Unity-Gain-Reset Opamps," IEEE Int. Workshop ADC Mod. Test., pp. 63-66, Sep. 2003.
• D. Chang and U. Moon, "A 0.9V 9mW 1MSPS Digitally Calibrated ADC with 75dB SFDR," IEEE VLSI Symposium, pp. 67-70, Jun. 2003.
• A. Pulincherry, M. Hufford, E. Naviasky, and U. Moon, "Continuous-Time Frequency Translating Bandpass Delta-Sigma Modulator," IEEE Int. Symp. Circuits Syst., vol. I, pp. 1013-1016, May 2003.
• J. Li and U. Moon, "An Extended Radix-Based Digital Calibration Technique for Multi-Stage ADC," IEEE Int. Symp. Circuits Syst., vol. I, pp. 829-832, May 2003.
• D. Bruneau, A. Early, U.Moon, and G. Temes, "High-Speed Switched Capacitor Filters Based on Unity-Gain Buffer," IEEJ Analog VLSI Workshop, pp. 5-9, Sep. 2002.
• M. Coe and U. Moon, "Mismatch-Shaping Successive Approximation ADC," IEEJ Analog VLSI Workshop, pp. 60-64, Sep. 2002.
• A. Rao, W. McIntyre, U. Moon, and G. Temes, "A Noise-Shaped Switched Capacitor DC-DC Voltage Regulator," IEEE European Solid-State Circuits Conf., pp. 375-378, Sep. 2002.
• X. Wang, P. Kiss, U. Moon, and G. Temes, "Digital Correlation Technique for the Estimation and Correction of DAC Errors in Multibit MASH ∆Σ ADCs," Int. Conf. Advanced A/D D/A Conv. Tech., pp. 39-42, Jun. 2002.
• M. Keskin, M. Brown, U. Moon, and G. Temes, "A Voltage-Mode Switched Capacitor Bandpass ∆Σ Modulator," Int. Conf. Advanced A/D D/A Conv. Tech., pp. 19-22, Jun. 2002.
• D. Chang, L. Wu and U. Moon, "Low-Voltage Pipelined ADC Using Opamp-Reset Switching Technique," IEEE Custom Integrated Circuits Conf., pp. 461-464, May 2002.
• S. Yoo, T. Oh, J. Moon, S. Lee and U. Moon, "A 2.5V 10b 120M Samples/s CMOS Pipelined ADC with High SFDR," IEEE Custom Integrated Circuits Conf., pp. 441-444, May 2002.
• J. Sonntag, J. Stonick, J. Gorecki, B. Beale, B. Check, X. Gong, J. Guiliano, K. Lee, B. Lefferts, D. Martin, U. Moon, A. Sengir, S. Titus, G. Wei, D. Wienlader and Y. Yang, "An Adaptive PAM-4 5Gb/s Backplane Transceiver in 0.25 m CMOS," IEEE Custom Integrated Circuits Conf., pp. 363-366, May 2002.
• J. Silva, X. Wang, P. Kiss, U. Moon and G. Temes, "Differential Techniques for Improved Delta-Sigma Data Conversion," IEEE Custom Int. Circuits Conf., pp. 183-186, May 2002.
• X. Wang, U. Moon, M. Liu, and G. Temes, "Digital Correlation Technique for the Estimation and Correction of DAC Errors in Multibit MASH ∆Σ ADCs," IEEE Int. Symp. Circuits Syst., vol. IV, pp. 691-694, May 2002.
• J. Li and U. Moon, "High-Speed Pipelined A/D Converter using Time-Shifted CDS Technique," IEEE Int. Symp. Circuits Syst., vol. I, pp. 909-912, May 2002.
• A. Rao, W. McIntyre, J. Parry, U. Moon, and G. Temes, "Buck-Boost Switched-Capacitor DC-DC Voltage Regulator using Delta-Sigma Control Loop," IEEE Int. Symp. Circuits Syst., vol. IV, pp. 743-746, May 2002.