Journal Papers

• I. Vytyaz, D. Lee, P. Hanumolu, U. Moon, and K. Mayaram, "Sensitivity analysis for oscillators," IEEE Trans. Computer-Aided Design, 2008.
• M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes, and U. Moon, "A 0.9V 92dB doubled-sampled switched-RC delta-sigma audio ADC," IEEE J. Solid-State Circuits, pp. 1195-1206, May 2008.
• P. Hanumolu, V. Kratyuk, G. Wei, and U. Moon, "A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter," IEEE J. Solid-State Circuits, pp. 414-424, Feb. 2008.
• P. Hanumolu, G. Wei, and U. Moon, " A wide-tracking range clock and data recovery circuit, IEEE J. Solid-State Circuits, pp. 425-439, Feb. 2008.
• T. Musah, B.R. Gregoire, E. Naviasky, and U. Moon, "Parallel correlated double sampling technique for pipelined analogue-to-digital converters," Electron. Lett., vol. 43, no. 23, Nov. 8, 2007.
• P. Kurahashi, P. Hanumolu, G. Temes, and U. Moon, "Design of low-voltage highly linear switched-R-MOSFET-C filters," IEEE J. Solid-State Circuits, pp. 1699-1709, Aug. 2007.
• R. Wang, S. Kim, S. Lee, S. You, J. Kim, U. Moon, and G. Temes, "A 100-dB gain-corrected delta-sigma audio DAC with headphone driver," Analog Int. Circuits Sig. Proc., vol. 51, pp. 27-31, Apr. 2007.
• T. Wu, K. Mayaram, and U. Moon, "An on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 775-783, Apr. 2007.
• B.R. Gregoire and U. Moon, "A sub 1-V constant Gm-C switched-capacitor current source," IEEE Trans. Circuits Syst. II, vol. 54, no. 3, pp. 222-226, Mar. 2007.
• V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram, "A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy," IEEE Trans. Circuits Syst. II, vol. 54, no. 3, pp. 247-251, Mar. 2007.
• V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram, "Frequency detector for fast frequency lock of digital PLLs," Electron. Lett., vol. 43, no. 1, pp. 13-14, Jan. 4, 2007.
• M. Brownlee, P. Hanumolu, K. Mayaram, U. Moon, "A 0.5-GHz to 0.5-GHz PLL with fully differential supply regulated tuning," IEEE J. Solid-State Circuits, pp. 2720-2728, Dec. 2006.
• N. Maghari, S. Kwon, G. Temes, and U. Moon, "Sturdy MASH delta-sigma modulator," Electron. Lett., vol. 42, no. 22, pp. 1269-1270, Oct. 26, 2006.
• J. Li, U. Moon, J. McNeill, M. Coln, and B. Larivee, "Comments on "Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC," (correspondence letter) IEEE J. Solid-State Circuits, pp. 1481, Jun. 2006.
  

Conference Proceedings

• D. Gubbins, B. Lee, P. Hanumolu, and U. Moon, "A continuous-time input pipeline ADC," IEEE Custom Int. Circuits Conf., Sep. 2008.
• I. Vytyaz, J. Carnes, T. Wu, P. Hanumolu, U. Moon, and K. Mayaram, "Noise tolerant oscillator design using perturbation projection vector analysis," IEEE Custom Int. Circuits Conf., Sep. 2008.
• P. Kurahashi, P. Hanumolu, and U. Moon, "A 1V downconversion filter using duty-cycle controlled bandwidth tuning," IEEE Custom Int. Circuits Conf., Sep. 2008.
• N. Maghari, S. Kwon, and U. Moon, "74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain," IEEE Custom Int. Circuits Conf., Sep. 2008.
• J. Jaussi, G. Balamurugan, J. Kennedy, F. O'Mahony, M. Mansuri, R. Mooney, B. Casper, and U. Moon, "In-situ jitter tolerance measurement technique for serial I/O," IEEE Symp. VLSI Circuits, Jun. 2008.
• O. Rajaee and U. Moon, " Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer," IEEE Int. Symp. Circuits Syst., pp. 1212-1215, May 2008.
• I. Vytyaz, D. Lee, U. Moon, and K. Mayaram, "Parameter variation analysis for voltage controlled oscillators in phase-locked loops," IEEE Int. Symp. Circuits Syst., pp. 716-719, May 2008.
• N. Maghari and U. Moon "Multi-loop efficient sturdy MASH delta-sigma modulators," IEEE Int. Symp. Circuits Syst., pp. 1216-1219, May 2008.
• B.R. Gregoire and U. Moon, "Reducing the effects of component mismatch by using relative size information," IEEE Int. Symp. Circuits Syst., pp. 512-515, May 2008.
• I. Vytyaz, P. Hanumolu, U. Moon, and K. Mayaram, "Periodic steady-state analysis augmented with design equality constraints," Design Auto. Test Europe (DATE), pp. 312-317, Mar. 2008.
• B.R. Gregoire and U. Moon, "An over-60dB true rail-to-rail performance using correlated level shifting and an ppamp with 30dB loop gain," IEEE Int. Solid-State Circuits Conf., pp. 540-541, Feb. 2008.
• O. Rajaee, N. Maghari, and U. Moon, "Time-shifted CDS enhancement of comparator-based MDAC for pipelined ADC applications," IEEE Int. Conf. Elec. Circuits Syst., pp. 210-213, Dec. 2007.
• J. Carnes, I. Vytyaz, P. Hanumolu, K. Mayaram, and U. Moon, "Design and analysis of noise tolerant ring oscillators using Maneatis delay cells," IEEE Int. Conf. Elec. Circuits Syst., pp. 494-497, Dec. 2007.
• S. Weaver, D. Knierim, and U. Moon, "Design considerations for stochastic analog-to-digital conversion," IEEE Int. Conf. Elec. Circuits Syst., pp. 234-237, Dec. 2007.
• I. Vytyaz, D. Lee, P. Hanumolu, U. Moon, and K. Mayaram, "Sensitivity analysis for oscillators," Int. Conf. Computer-Aided Design (ICCAD), pp. 458-463, Nov. 2007.
• R. Desikachari, M. Steeds, J. Huard, and U. Moon, "An efficient design procedure for high-speed low-power dual-modulus prescalers," IEEE Int. Conf. Elec. Circuits Syst., pp. 645-648, Dec. 2007.
• J. Carnes, G. Ahn, and U. Moon, "A 1V 10b 60MS/s hybrid opamp-reset/switched-RC pipelined ADC," IEEE Asian Solid-State Circuits Conf., pp. 236-239, Nov. 2007.
• N. Sasidhar, Y. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. Hanumolu, and U. Moon, " A 1.8V 36mW 11bit 80MS/s pipelined ADC using capacitor and opamp sharing," IEEE Asian Solid-State Circuits Conf., pp. 240-243, Nov. 2007.
• Y. Kook, J. Li, B. Lee, and U. Moon, " Low-power and high-speed pipelined ADC using time-aligned CDS technique," IEEE Custom Int. Circuits Conf., pp. 321-324, Sep. 2007.
• G. Ahn, M. Kim, P. Hanumolu, and U. Moon, "A 1V 10b 30MSPS switched-RC pipelined ADC," IEEE Custom Int. Circuits Conf., pp. 325-328, Sep. 2007.
• M. Brownlee, P. Hanumolu, and U. Moon, "A 3.2Gb/s oversampling CDR with improved jitter tolerance," IEEE Custom Int. Circuits Conf., pp. 353-356, Sep. 2007.
• V. Kratyuk, P. Hanumolu, K. Mayaram, and U. Moon, "A 0.6GHz to 2GHz digital PLL with wide tracking range," IEEE Custom Int. Circuits Conf., pp. 305-308, Sep. 2007.
• P. Hanumolu, G. Wei, U. Moon, and K. Mayaram, "Digitally-enhanced phase-locking circuits," IEEE Custom Int. Circuits Conf., pp. 361-368, Sep. 2007.
• T. Wu, P. Hanumolu, K. Mayaram, and U. Moon, "A 4.2 GHz PLL frequency synthesizer with an adaptively tuned coarse loop," IEEE Custom Int. Circuits Conf., pp. 547-550, Sep. 2007.
• V. Sharma, U. Moon, and G. Temes, "Efficient pipelined ADCs using integer gain MDACs," IEEE PRIME, pp. 1-4, Jul. 2007.
• I. Vytyaz, D. Lee, S. Lu, A. Mehrotra, U. Moon, and K. Mayaram, "Parameter finding methods for oscillators with a specified oscillation frequency," Design Automation Conference (DAC), pp. 424-429, Jun. 2007.
• S. Kwon and U. Moon, "A high-speed delta-sigma modulator with relaxed DEM timing requirement," IEEE Int. Symp. Circuits Syst., pp. 733-736, May 2007.
• B.R. Gregoire and U. Moon, "Process-independent resistor temperature-coefficients using series/parallel and parallel/series composite resistors," IEEE Int. Symp. Circuits Syst., pp. 2826-2829, May 2007.
• N. Maghari, S. Kwon, G. Temes, and U. Moon, "Mixed-order sturdy MASH delta-sigma modulator," IEEE Int. Symp. Circuits Syst., pp. 257-260, May 2007.
• I. Vytyaz, D. Lee, A. Mehrotra, U. Moon, and K. Mayaram, "Periodic steady-state analysis of oscillators with a specified oscillation frequency," IEEE Int. Symp. Circuits Syst., pp. 1073-1076, May 2007.