MISSION STATEMENT: SUSTAINABLE SILICON
The VLSI research group is exploring novel VLSI circuit and system architectures that enable significant
improvements in energy efficiency.
Energy-Efficient VLSI Interconnect --
Extreme-scale computing will enable massive parallelism on multiple vertical levels, from thousands
of computational units on a single processor to thousands of processors in a single data
center. Unfortunately, the energy required to communicate between these units at every level (onchip,
off-chip, off-rack) will be the critical limitation to energy efficiency (DARPA Exascale Computing Study, 2008).
We are developing technologies for energy-efficient interconnect: wireline communications, wireless RF circuits,
on-chip router links and crossbars, analog-digital converters.
Energy-Constrained Medical Sensors --
Future implantable and external medical electronics are limited antagonistically by both energy-efficiency and robustness. Energy efficiency results in reduced overhead in battery maintenance and smaller form factor, while system robustness is required to guarantee patient health. We are currently building medical sensors that can
adaptively achieve both requirements.
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October 2009:
Congrats to Jacob, Karthik, Jing-Guang, and Charles for 1st-pass
working silicon!
July 2009:
Joint paper (with Institute of Computing Technology, Chinese Academy of Sciences) is accepted at Asian Solid-State Circuits Conference 2009
Good work, Divya, for the 90-CMOS tapeout!
Won Best Faculty Project award from NSF Industry-University Research Center--CDADIC (Center for Digital/Analog Design of Integrated Circuits)
Doctoral student Kang-Min Hu doing summer internship project on low-power links at Montage Technology, in Shanghai, China.
Doctoral student Jacob Postman doing summer research project on multicore as NSF fellow at Institute of Computing Technology, Chinese Academy
of Sciences in Beijing, China.
Awarded $540k NSF Grant (with Professors Liu/Nguyen) for Next-Generation RF Circuits and Systems for
Future Computer Systems, collaborating with Intel as GOALI partner
May 2009:
DFE-embedded SRAM (Jon and Ming) and Asynchronous sub-threshold logic (Robert and Joe) 0.18um CMOS tapeouts with Professor Chi (Tsinghua)
Good work, Tao and Charles, for taping out the 40nm-CMOS chips!
April 2009:
Congratulations to Jacob, Chris, and Kang-Min (OSU) and Tushar and Prof. Peh (Princeton) for
finishing the tapeout of the 90nm-CMOS, 4-core, Network-on-a-Chip
March 2009:
Congratulations to Jacob for getting the NOCHI paper (with Li-Shiuan Peh of Princeton and Mattan Erez of UT-Austin) accepted into IEEE-Micro
Congratulations to Kang-Min for getting the 0.6mW/Gbps high-speed I/O chip accepted into the 2009 VLSI Circuits Symposium!
February 2009:
Looking for a few excellent undergrads for paid undergraduate research; specifially, to work and
test experimentally some prototype test-chips in the lab, collecting data, eventually to publish a research paper
January 2009:
Published a number of joint papers with Professor Baoyong Chi (Tsinghua University, China)
and Professor Weiwu Hu (Chinese Academy of Sciences, China).
Congratulations to Kang-Min, Tao Jiang, and Divya! All three papers accepted to ISCAS 2009.
Happy New Year for 2009. Hope to have a lot of really cool stuff for the new year.
December 2008
Congrats to Jing-Guang and Kang-Min. The 90nm CMOS test-chips seem to be working remarkably well!
Two papers accepted at VLSI - DAT conference, April 2009. Congratulations Charles and Karthik.
Visiting ITRI(Taipei), Chinese Academy of Sciences (Beijing), Tsinghua (Beijing), Shanghai JiaoTong (Shanghai), Fudan (Shanghai)
Kang-Min measuring chip at LSI (Mipitas, CA)
November 2008
Jing-Guang successfully defends M.S. thesis. Good luck at Broadcom!
Talk at Santa Barbara
October 2008
Meeting on SAR-ADC at LSI-Logic
Three 90nm chips testing now. Looking good!
Four papers submitted to ISCAS
One paper submitted to VLSI-DAT
September 2008:
Visit to ST-Micro in Crolles, France
Looking for a grad or advanced undergrad with experience in LabView,
data acquisition, and testchip/computer test scan interfaces
Looking for enthusiastic, ambitious students
looking to work on two possible senior design projects
One tapeout in 90nm CMOS: UWB transceiver
New website is up and running
New students Jacob and Divya join!
August 2008:
Two chips taped out in 0.18um CMOS
New paper presented at Hot Interconnect 2008.
Press's review of the Paper in Electronics
Design News
June 2008:
Three new tapeouts in 90nm CMOS: phase calibration; low-power, 10Gbps receivers; low-power,
DFEs and injection-locked ring oscillators
September 2007:
Four tapeouts in 65nm CMOS
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