| Title | Date | Designer | Collaborators | Technology | Chip Image |
| Sub-0.6mW/Gbps, 6.4-8Gbps Serial Link Receiver |
Dec. 2008 |
Kang-Min Hu (PhD) |
Intel Circuits Research Laboratory
| 90nm-CMOS |
 |
| 500Mbps, 182pJ/b UWB-RF Transceiver |
July 2009 |
Charles Hu (PhD) |
Intel DEG |
90nm-CMOS |
 |
| Four-Core, Network-on-a-Chip with Energy-Efficient On-Die Interconnect |
Sep. 2009 |
Jacob Postman (PhD) |
Li-Shiuan Peh (MIT) |
90nm-CMOS |
 |
| On-Die, Multi-Phase Timing Calibration |
Nov. 2008 |
Jing-Guang Wang (MS) |
Chinese Academy of Sciences, Intel CRL |
90nm-CMOS |
 |
| Reconfigurable, Dynamic Voltage-Scaling 2.4GHz LNA
| Sep. 2009 |
Karthik Jayaraman (MS) |
Tsinghua University, China | 180nm-CMOS
 |