VLSI Research Group
PUBLICATIONS

  1. 3D-Sensing, Robotic-Computer Vision, and Deep Learning
  2. Multi-Gigahertz Photonics and Wireline
  3. Energy-Efficient VLSI Architectures and Digital Circuits
  4. Short-Range, Low-Power Ultrawideband/Wireless Transceivers
  5. IOT Sensing


(0) 3D-Sensing, Robotic-Computer Vision, and Deep Learning

A. Selected Publications

  • V. Behravan, G. Singh, and P. Y. Chiang, "Adaptive Compressive-Sensing of 3D Point Clouds", accepted, IEEE International Conference on Signal and Image Processing, 2017.

  • V. Behravan, G. Singh, and P. Y. Chiang, "A Framework For Compressive-Sensing of 3D Point Clouds", accepted, International Conference on Computational Intelligence and Security, 2016.

    (1) Multi-Gigahertz Photonics and Wireline

    A. Selected Publications

  • [C38] Q. Nan, et. al., "A 51Gb/s, 320mW, PAM4 CDR with Baud-Rate Sampling for High-Speed Optical Interconnects", accepted, IEEE Asian Solid-State Circuits Conference, 2017.

  • [C38] B. Yin, et. al., "A 32Gb/s-NRZ, 15GBaud/s-PAM4 DFB Laser Driver with Active Back-Termination in 65nm CMOS", accepted, IEEE RFIC Symposium, 2017.

  • [J16] N. Qi, et. al.,"Co-Design and Demonstration of a 25Gb/s Silicon-Photonic Mach-Zehnder Modulator with a CMOS-Based High-Swing Driver", accepted, IEEE Journal of Selected Topics in Quantum Electronics, 2016.

  • [J15] K. Yu, et. al., "A 25Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver with Microring Wavelength Stabilization", accepted, IEEE Journal of Solid-State Circuits, 2016.

  • [C37] G. Hui, et. al., "A 25Gb/s 30dB Limiting Amplifier Using Stacked Inductors", accepted, IEEE Optical Interconnects Conference, 2016.

  • [C36] Q. Yang, et. al., "A 4 x 10-25Gbps Low Noise TIA Design in 65nm CMOS for Optical Serial Link", accepted, IEEE Optical Interconnects Conference, 2016.

  • [C35] J. Shi, et. al., "A Low-Cost, System-on-Chip for Optical Time Domain Reflectometry (OTDR)", accepted, IEEE International Wireless Symposium (IWS), 2016.

  • [C34] N. Qi, et. al., "A 32Gb/s NRZ, 25GBaud/s PAM4 Reconfigurable, Si-Photonic MZM Transmitter in CMOS", accepted, Optical Fiber Conference (OFC), 2016.

  • [J14] L. Hao, et. al., "A 25Gb/s, 4.4V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65nm CMOS", accepted, IEEE Journal of Solid-State Circuits, 2016.

  • [C33] S. Palermo, et. al., "Silicon Photonic Microring Resonator-Based Transceivers for Compact WDM Optical Interconnects", Compound Semiconductor IC Symposium, accepted, 2015.

  • [C32] J. Wang, N. Qi, Z. Wang, Q. Yang, H. Guo, R. Bai, Z. Hong, P. Y. Chiang, "4 x 30 Gbps 155mW/Channel VCSEL Driver in 65nm CMOS", Optical Interconnects Conference, April-2015.

  • [C31] Z. Wang, R. Bai, H. Li, J. Wang, N. Qi, Z. Hong, P. Chiang, "A 30mW/Channel 4x25Gbps Baud-Rate Bang-Bang CDR Using an Integrating Receiver Based Data Sampling", Optical Interconnects Conference, April-2015.

  • [C30] Q. Nan, X. Li, H. Li, X. Xiao, L. Wang, Z. Li, Y. Yu, P. Chiang, "A 25Gb/s, 520mW, Silicon-Photonic Mach-Zehnder Modulator with Distributed Driver in CMOS", Optical Fiber Conference (OFC), 2015.

  • [C29] K. Yu, et. al. "25Gb/s Hybrid-Integrated Silicon Photonic Receiver with Microring Wavelength Stabilization ", accepted, Optical Fiber Conference (OFC), 2015.

  • [J13] Q. Pan, et. al. "A 30-Gb/s 1.37-pJ/bit CMOS Receiver for Optical Interconnects", accepted, IEEE Journal of Lightwave Technology, 2015. pdf

  • [C28] K. Yu, H. Li, A. Titriku, B. Wang, A. Shafik, C. Li, Z. Wang, R. Bai, C.H. Chen, M. Fiorentino, P. Y. Chiang, and S. Palermo, "A 24Gbs, 0.71pJ/bit, Si-Photonic Source-Synchronous Receiver with Adaptive Equalization and Microring Wavelength Stabilization", accepted, ISSCC-2015.

  • [C27] H. Li, Z. Xuan, A. Titrku, K. Yu, B. Wang, N. Qi, A. Shafik, C. Li, M. Fiorentino, M. Hochberg, S. Palermo, P. Y. Chiang, "A 5 x 25Gbs, 4.4V Swing, AC-Coupled, Si-Photonic Microring Transmitter with 2-Tap Asymmetric FFE and Dynamic Thermal Tuning in 65nm CMOS", accepted, ISSCC-2015.

  • [J12] Y. Song, H. Yang, H. Li, P. Y. Chiang, S. Palermo, "An 8-16Gb/s, 0.65-1.05pJ/b, Voltage-Mode Transmitter with Analog Impedance Modulation Equalization and sub-3ns Power-State Transitioning", accepted, JSSC, 2015. pdf

  • [C26] Quan Pan, Yipeng Wang, Zhengxiong Hou, Li Sun, Yan Lu, Liang Wu, Wing-Hung Ki, Patrick Chiang, and C. Patrick Yue, "A 41-mW 30-Gb/s CMOS Optical Receiver with Digitally-Tunable Cascaded Equalization", accepted, European Solid-State Circuits Conference, 2014.

  • [J11] C. Li, R. Bai, A. Shafik, E. Tabasy, B. Wang, G. Tang, C. Ma, C.H. Chen, Z. Peng, M. Fiorentino, R. Beausoleil, P. Chiang, and S. Palermo, "Silicon Photonic Transceiver Circuits with Ring Resonator Bias-Based Wavelength Stabilization in 65-nm CMOS", IEEE Journal of Solid-State Circuits, 2014. pdf

  • [C25] J. Wang, L. Sun, Z. Wang, Q. Nan, P. Y. Chiang, Z. Hong, "25 Gb/s VCSEL Driver with Pulse Equalization Technique", accepted, IEEE Optical Interconnects Conference, 2014. pdf

  • [C24] J. Chen, A. Ayman, M. Fiorentino, P. Y. Chiang, S. Palermo, and R. Beausoleil, "A WDM Silicon Photonic Transmitter based on Carrier-Injection Microring Modulators", accepted, IEEE Optical Interconnects Conference, 2014. pdf

  • [C23] H. Li, S. Chen, L. Yang, R. Bai, W. Hu, F.Y. Zhong, S. Palermo, P. Y. Chiang,"A 0.8V, 560fJ/bit, 14Gb/s Injection-Locked Receiver with Input Duty-Cycle Distortion Tolerable Edge-Rotating 5/4X Sub-Rate CDR in 65nm CMOS", accepted, VLSI Circuits Symposium, 2014. pdf

  • [C22] Z. Wang, R. Bai, J. Wang, X. Jing, Q. Nan, L. Sun, C. P. Yue, Z. Hong, and P.Y. Chiang, "A 25Gbps, 2x-Oversampling CDR Using a Zero-Crossing Linearizing Phase Detector", accepted, RFIC Symposium, 2014. pdf

  • [C21] Y-H. Song, H-W. Yang, H. Li, P. Y. Chiang, S. Palermo, "An 8-to-16Gb/s 0.65-to-1.05pJ/b 2-Tap Impedance-Modulated Voltage-Mode Transmitter with Fast Power-State Transitioning in 65nm CMOS", International Solid-State Circuits Conference, Feb. 2014. pdf

  • [C20] R. Bai, S. Palermo, and P. Y. Chiang, "A 0.25pJ/b 0.7V 16Gb/s 3-Tap Decision-Feedback Equalizer in 65nm CMOS", International Solid-State Circuits Conference, Feb. 2014. pdf

  • [C19] Shuai Chen, Hao Li, Liqiong Yang, Zongren Yang, Weiwu Hu and Patrick Yin Chiang, "A 1.2 pJ/b 6.4 Gb/s 8+1-Lane Forwarded-Clock Receiver with PVT-Variation-Tolerant All-Digital Clock and Data Recovery in 28nm CMOS", Custom Integrated Circuits Conference (CICC), San Jose, Sep. 2013. pdf

  • [C18]Chin-Hui Chen, Cheng Li, Rui Bai, Ayman Shafik, Marco Fiorentino, Zhen Peng, Patrick Chiang, Samuel Palermo, and Ray Beausoleil, "Hybrid Integrated DWDM Silicon Photonic Transceiver with Self-Adaptive CMOS Circuits", accepted, Optical Interconnects Conference, May 2013. pdf

  • [J10] Y. Song, R. Bai, N. Yang, K. Hu, P. Chiang, and S. Palermo, "A 0.47-0.66pJ/bit, 4.8-8Gb/s I/O Transceiver in 65nm-CMOS", IEEE Journal of Solid-State Circuits, May 2013. pdf

  • [C17] C. Li, R. Bai, A. Shafik, E. Tabasy, G. Tang, C. Ma, C-H. Chen, Z. Peng, M. Fiorentino, P. Chiang, S. Palermo, "A Ring-Resonator-Based Silicon Photonics Transceiver with Bias-Based Wavelength Stabilization and Adaptive Power-Sensitivity Receiver", ISSCC, Feb. 2013. pdf

  • [J9] T. Jiang, K. Hu, W. Liu, F. Zhong, C. Zhong, and P. Chiang, "A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation (SAR) ADC with Improved Feedback Delay in 40nm-CMOS", accepted, IEEE Journal of Solid-State Circuits, 2012. pdf

  • [J8] K. Hu, R. Bai, T. Jiang, C. Ma, A. Ragab, S. Palermo, and P. Chiang, "0.16-0.25pJ/bit, 8Gb/s Near-Threshold Serial Link Receiver with Super-Harmonic Injection-Locking" IEEE Journal of Solid-State Circuits, August 2012. pdf

  • [C16] K. Hu, T. Jiang, S. Palermo, and P. Chiang, "Low-Power 8Gb/s Near-Threshold Serial Link Receivers Using Super-Harmonic Injection Locking in 65nm CMOS", IEEE Custom Integrated Circuits Conference, San Jose, CA, Sep. 2011. pdf

  • [J7] Lingli Xia, Jingguang Wang, Will Beattie, Jacob Postman, and Patrick Yin Chiang, "Sub-2ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits", IEEE Transactions on Circuits and System-I, August 2011. pdf

  • [J6] R. Bai, J. Wang, L. Xia, F. Zhang, Z. Yang, W. Hu, P. Chiang, "Sinusoidal Clock Sampling for Multi-Gigahertz ADCs", IEEE Transactions on Circuits and System-I, July 2011. pdf

  • [J5] K. Hu, L. Wu, and P. Chiang, "A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis", IEEE Transactions on VLSI Systems, May 2011. pdf

  • [C15] T. Jiang, W. Liu, C. Zhong, F. Zhong, P. Chiang, "Single-Channel, 1.25-GS/s, 6-bit, Loop-Unrolled Asynchronous SAR-ADC in 40nm-CMOS", IEEE Custom Integrated Circuits Conference, Sep. 2010. (Intel/CICC Student Scholarship Award) pdf

  • [J4] K. Hu, T. Jiang, J.G. Wang, F. O'Mahony, and P. Chiang, "A 0.6mW/Gbps, 6.4-7.2Gbps Serial Link Receiver Using Local, Injection-Locked Ring Oscillators in 90nm CMOS", Journal of Solid-State Circuits, April 2010. pdf

  • [C14] Z. Feng, Y. Yi, Y. Zongren, P. Chiang, W. Hu, "A Low Latency Transceiver Macro with Robust Design Technique for Processor Interface", IEEE Asian Solid-State Circuits Conference, November 2009. pdf

  • [C13] K. Hu, T. Jiang, J.G. Wang, F. O'Mahony, and P. Chiang, "A 0.6mW/Gbps, 6.4-8.0Gbps Serial Link Receiver Using Local, Injection-Locked Ring Oscillators in 90nm CMOS", IEEE VLSI Circuits Symposium, Kyoto, Japan, June 2009. pdf

  • [J3] Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer. IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, April 2005, pp. 1004-1011.

  • [C12] Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer. IEEE Symposium on VLSI Circuits, June 15-19, 2004, pp. 272-275.
  • [C11] Ming-Ju E. Lee, William J. Dally, John W. Poulton, Patrick Chiang, Stephen F. Greenwood. An 84-mW 4Gb/s Clock and Data Recovery Circuit for Serial Link Applications. IEEE VLSI Circuits Symposium, Kyoto, Japan, June 2001, pp. 149-152. pdf

  • [J2] Ming-Ju E. Lee, William Dally, Patrick Chiang. Low-Power Area-Efficient High-Speed I/O Circuit Techniques. IEEE Journal of Solid-State Circuits, November 2000, Vol. 35, No. 11, pp. 1591-1599.

  • [C10] Ming-Ju E. Lee, William Dally, Patrick Chiang. A 90mW 4Gb/s Equalized I/O Circuit with Input Offset Cancellation. International Solid State Circuits Conference, San Francisco, February 2000, TP 15.3, pp. 252-253.
  • [C9] Cormac Conroy, Samuel Sheng, Arnold Feldman, Greg Uehara, Albert Yeung, Chih-Jen Hung, Vivek Subramanian, Patrick Chiang, Paul Lai, Xiaomin Si, Jerry Fan, David Flynn, Meiqing He. A CMOS Analog Front-End IC for DMT ADSL. International Solid State Circuits Conference, San Francisco, February 1999, pp. 240-241.
  • B. Other Publications

  • S. Palermo, et. al., "Adaptive gain, equalization, and wavelength stabilization techniques for silicon photonic microring resonator-based optical receivers", accepted, Proceedings of SPIE, 2016.

  • S. Chen, et. al., "A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and Data Recovery in 28nm CMOS for High-Density Interconnects", accepted, IEEE Transactions on Very Large Scale Integration Systems, 2015.

  • T. Jiang, et. al., "14.4-GS/s, 5-bit, 50mW Time-Interleaved ADC with Distributed Track-and-Hold and Sampling Instant Synchronization for ADC-Based SerDes", accepted, IWS, 2015.

  • B. Querbach, et. al., "Comparison of Hardware Based and Software Based Stress Testing of Memory IO Interface", Midwest Symposium on Circuits and Systems, Aug. 2013. pdf

  • [C8] T. Jiang, P. Y. Chiang, and K. Hu "A Low-Power, Capacitively-Divided, Ring Oscillator with Digitally Adjustable Voltage Swing," VLSI-DAT, Hsinchu, Taiwan, 2012. pdf

  • [J1] A. Ragab, Y. Liu, K. Hu, P. Chiang, and S. Palermo, "Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links," special issue on Clock/Frequency Generation Circuits and Systems, Journal of Electrical and Computer Engineering, 2011. pdf

  • [C7] T. Jiang and P. Chiang, "Energy-Efficient, Decision Feedback Equalization Using SAR-Like Capacitive Charge Summation," VLSI-DAT, Hsinchu, Taiwan, April 2010. pdf

  • [C6] T. Jiang and P. Chiang, "Design Techniques Enabling 10+ GSs, 6b, 100mW ADCs," SRC Techcon 2009, Sep. 2009.

  • [C5] G. Zhuo, P. Chiang, and W. Hu, "A 10Gbps/ Wire-line Transceiver with Half Rate Period Calibration CDR", IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009. pdf

  • [C4] G. Zhuo, D. Kesharwani, P. Chiang, and W. Hu, "Measuring and Compensating for Process Mismatch Induced, Reference Spurs in Phase-Locked Loops Using a Sub-Sampled DSP", IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009. pdf
  • [C3] Tao Jiang and P. Chiang, "Sense Amplifier Power and Delay Characterization for Operation Under Low-Vdd and Low-Voltage Clock Swing", IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009. pdf

  • [C2] Kang-Min Hu and P. Chiang, "Comparison of on-Die Global Clock Distribution Methods for Parellel Serial Links", IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009. pdf

  • [C1] Patrick Chiang, William J. Dally, Ming-Ju E. Lee. A 20Gb/s 0.13um CMOS Serial Link, Hotchips 2002, Stanford, CA, Aug. 18-20, 2002.
  • [P2] T. Jiang, P. Y. Chiang, and F. Y. Zhong, "Time-Interleaved Track-and-Hold Circuit Using Distributed Global Sine-Wave Clock", US Patent Number 8487795-B1, Issued Jul 16, 2013. pdf


    (2) Energy-Efficient VLSI Architectures and Digital Circuits

    A. Selected Publications

  • [J7] B. Querbach, et. al., "Architecture of a Reusable BIST Engine for Detection and Auto Correction of Memory failures and for IO debug, validation, link training, and power optimization on 14nm 3DS SOC", accepted, IEEE Design & Test, 2015.

  • [C17] R. Pawlowski, J. Crop, M. Cho, J. Tschanz, V. De, T. Fairbanks, H. Quinn, S. Borkar, and P.Y. Chiang, "Characterization of Radiation-Induced SRAM and Logic Soft Errors from 0.33V to 1.0V in 65nm CMOS", accepted, CICC, 2014. pdf

  • [C16] R. Pawlowski, J. Crop, M. Cho, J. Tschanz, V. De, S. Borkar, T. Fairbanks, H. Quinn, P. Chiang "A Reference Design for Effective Characterization of Soft Error Vulnerability of Ultra-low Voltage Logic and Memory Circuits", accepted, SELSE Workshop, 2014. pdf

  • [C15] J. Crop, E. Krimer, P. Chiang, M. Erez, "Replication-Free Single-Event Upset (SEU) Detection for Eliminating Silent Data Corruption in CMOS Logic", accepted, SELSE Workshop, 2013. pdf
  • [J5] J. Postman, T. Krishna, C. Edmonds, L.S. Peh, and P. Y. Chiang, "SWIFT: A Low-Power Network-On-Chip implementing the Token Flow Control Router Architecture with Swing-Reduced Interconnects", accepted, IEEE Transactions on VLSI Systems, 2013. pdf

  • [C14] E. Krimer, P. Chiang, and M. Erez, "Lane Decoupling for Improving the Timing-Error Resiliency of Wide-SIMD Architectures", International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012. pdf

  • [C13] J. Crop, R. Pawlowski, and P. Chiang, "Regaining Throughput Using Completion Detection for Error-Resilient, Near-Threshold Logic", Design Automation Conference (DAC), 2012. pdf

  • [C12] Robert Pawlowski, Evgeni Krimer, Joseph Crop, Jacob Postman, Nariman Moezzi-Madani, Mattan Erez, Patrick Chiang, "A 530mV 10-Lane SIMD Processor With Variation Resiliency in 45nm SOI", Feb., ISSCC-2012. pdf

  • [J4] Joseph Crop, Evgeni Krimer, Nariman Moezzi-madani, Thomas Ruggeri, Robert Pawlowski, Patrick Chiang, Mattan Erez, "Error Detection and Recovery Techniques for Variability-Aware CMOS Computing: A Comprehensive Review", Special Issue on Low Power Design and Methodologies and Applications, Journal of Low Power Electronics and Applications, 2011. pdf

  • [C11] J. Postman and P. Chiang, "Energy-Efficient Transceiver Circuits for Short-Range On-chip Interconnects", IEEE Custom Integrated Circuits Conference, San Jose, CA, Sep. 2011. pdf

  • [C10] N. Moezzi-Madani, T. Thorolfsson, J. Crop, P. Chiang, W.R. Davis, "An Energy-Efficient 64-QAM-MIMO Detector for Emerging Wireless Standards", Design, Automation, and Test of Europe (DATE), March 2011. pdf

  • [C9] T. Krishna, J. Postman, L.- S. Peh, P. Chiang, "SWIFT: A SWing-reduced Interconnect For a Token-based Network-on-Chip in 90nm CMOS", International Conference on Computer Design (ICCD), Amsterdam, Netherlands, October 2010. pdf

  • [J3] E. Krimer, R. Pawlowski, M. Erez, P. Chiang, "Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications", IEEE Computer Architecture Letters, Jan/June 2010. pdf

  • [J2] T. Krishna, A. Kumar, J. Postman, M. Erez, P. Chiang, and L. Peh, "Express Virtual Channels with Capacitively Driven Global Links", IEEE Micro, July/August 2009. pdf

  • [C8] Tushar Krishna, Amit Kumar, Patrick Chiang, Mattan Erez and Li-Shiuan Peh, " NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication " Proceedings of Hot Interconnects (HOTI), Stanford, California, August 2008. pdf

    B. Other Publications

  • [C8] B. Querbach, R. Khanna, D. Blankenbeckler, Y. Zhang, R. Anderson, S. Deyati, and P. Chiang, "A Reusable BIST with Software Assisted Repair Technology improved Memory and IO debug, validation and test time", accepted, International Test Conference (ITC), 2014. pdf

  • [C7] Eric Donkoh and Patrick Chiang, "A Low-Leakage Dynamic Register File with Unclocked Wordline and Sub-Segmentation for Improved Bitline Scalability," accepted, ISPLED 2012. pdf

  • [C6] Eric Donkoh, Teck Siong Ong, Yan Nee Too and Patrick Chiang, "Register File Write Data Gating Techniques and Break-Even Analysis Model," accepted, ISPLED 2012. pdf

  • [C5] J. Postman and P. Chiang, "A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations", accepted, ISRN Electronics, 2012. pdf

  • [C4] D. Ba, P. Chiang, and T. Nguyen, "Network Coding in Multicore Processors", accepted, IEEE International Performance Computing and Communications Conference (IPCC-2011). pdf

  • [C3] B. Goska, J. Postman, M. Erez, P. Chiang, "Hardware/software co-design for energy-efficient parallel computing," Department of Energy SciDAC Conference, July 2011. pdf

  • [C2] Joseph Crop, Robert Pawlowski, Nariman Moezzi-Madani, Jarrod Jackson and Patrick Chiang, "Design Automation Methodology for Improving the Variability of Synthesized Digital Circuits Operating in the Sub/Near-Threshold Regime," Workshop on Low-Power System on Chip (SoC), 2nd Green Computing Conference, Orlando, FL, July 2011. pdf

  • [J1] N. Moezzi-Madani, T. Thorolfsson, P. Chiang and W. R. Davis, "Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding," Journal of Signal Processing Systems -- Springer, May 2011. pdf
  • [C1] J. Crop, S. Fairbanks, R. Pawlowski, and P. Chiang, "150mV Sub-Threshold Asynchronous Multiplier for Low-Power Sensor Applications", VLSI-DAT, Hsinchu, Taiwan, April 2010. pdf

  • [P3] J. Postman, P. Y. Chiang, "Low-Voltage Swing Circuit Modifications", US Patent #20140040843-A1, Issued Feb 6, 2014. pdf

    (3) Short-Range, Low-Power Ultrawideband/Wireless Transceivers

    A. Selected Publications

  • [J14] J. Kang, S. Rao, P. Chiang and A. Natarajan, "Design and Optimization of Area-Constrained Wirelessly Powered CMOS UWB SoC for Localization Applications," in IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 4, pp. 1042-1054, April 2016.

  • [C13] J. Kang, P. Y. Chiang, and A. Natarajan, "A 1.2cm2 2.4GHz Self-Oscillating Rectifier-Antenna Achieving -34.5dBm Sensitivity for Wirelessly Powered Sensors", accepted, ISSCC 2016.

  • [C12] J. Kang, P. Y. Chiang, and A. Natarajan, "A 3.6 cm2 Wirelessly-Powered UWB SoC with -30.7dBm Rectifier Sensitivity and sub-10cm Range Resolution", accepted, IEEE RFIC Symposium, 2015.

  • [J12] J. Cheng, Q. Nan, P. Y. Chiang, and A. Natarajan, "A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65nm CMOS", accepted, IEEE Journal of Solid-State Circuits, 2014. pdf

  • [C11] J. Cheng, N. Qi, P. Y. Chiang, A. Natarajan, "A 1.3mW 0.6V WBAN-Compatible Sub-Sampling PSK Receiver in 65nm CMOS", International Solid-State Circuits Conference, Feb. 2014. pdf

  • [J11] Nan Qi, Yang Xu, Ni Xu, Baoyong Chi, Yang Xu, Xiaobao Yu, Xing Zhang, Patrick Chiang, Woogeun Rhee, Zhihua Wang, "A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65nm CMOS with On-Chip I/Q Calibration", IEEE Transactions on Circuits and Systems-I, 2012. pdf

  • [C10] C. Hu and P. Chiang, "All-Digital 3-50 GHz Ultra-wideband Pulse Generator for Short-range Wireless Interconnect in 40nm CMOS", IEEE Custom Integrated Circuits Conference, San Jose, CA, Sep. 2011. pdf

  • [J10] L. Xia, K. Shao, H. Chen, Y. Huang, Z. Hong, and P. Chiang, "0.15nJ/b 3-5GHz IR-UWB System with Spectrum Tunable Transmitter and Merged-Correlator Noncoherent Receiver", IEEE Transactions on Microwave Theory and Techniques, April 2011. pdf

  • [J9] S. Redfield, S. Woracheewan, H. Liu, P. Chiang, J. Nejedlo, R. Khanna, "Understanding the Ultrawideband Channel Characteristics within a Computer Chassis", IEEE Antennas and Wireless Propagation Letters, February 2011. pdf

  • [J8] C. Hu, R. Khanna, J. Nejedlo, K. Hu, H. Liu, P.Y. Chiang, "90nm-CMOS, 500Mbps, 3-5GHz Fully-Integrated IR-UWB Transceiver with Multi-Path Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization", IEEE Journal of Solid-State Circuits, May 2011. pdf

  • [J7] P. Chiang, S. Woracheewan, C. Hu, L. Guo, R. Khanna, J. Nejedlo, and H. Liu, "Short-Range, Wireless Interconnect Within a Computing Chassis: Design Challenges", IEEE Design and Test of Computers, Vol. 27, No. 4, July/August 2010. pdf
  • [J6] P. Chiang, Changhui Hu, "Chaotic Pulse-Position Baseband Modulation for an Ultra-wideband Transceiver in CMOS", IEEE Transactions on Circuits and Systems-II, June 2010. pdf

  • [C9] Karthik Jayaraman, Qadeer Khan, Baoyong Chi, William Beattie, Zhihua Wang, and Patrick Chiang, "A Self-Healing 2.4GHz LNA with On-Chip S11/S21 Measurement/Calibration for In-Situ PVT Compensation," IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Anaheim, CA, 2010. pdf

  • [C8] Changhui Hu, Rahul Khanna, Jay Nejedlo, Kangmin Hu, Huaping Liu, and Patrick Y. Chiang, "A 90nm-CMOS, 500Mbps, Fully-Integrated IR-UWB Transceiver Using Pulse Injection-Locking for Receiver Phase Synchronization", IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2010. pdf

  • [J5] B. Chi, J. Yao, P. Chiang, and Z. Wang, "A 0.18um CMOS GFSK Analog Front-End Using a Bessel-Based Quadrature Discriminator with On-Chip Automatic Tuning", IEEE Transactions on Circuits and Systems I: Regular Papers, Nov. 2009. pdf

    B. Other Publications

  • [J5] B. Zhou and P. Chiang, "Short-Range Low-Data-Rate FM-UWB Transceivers: Overview, Analysis, and Design," TCAS-I, Mar. 2016.

  • [C8] J. Kang, S. Rao, P. Chiang and A. Natarajan, "Area-constrained wirelessly-powered UWB SoC design for small insect localization," 2016 IEEE Topical Conference on Wireless Sensors and Sensor Networks (WiSNet), Austin, TX, 2016, pp. 18-20.

  • [J4] 5.Y. Xu, B. Chi, X. Yu, N. Qi, P. Chiang, and Z. Wang, "Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver," IEEE Transactions on Circuits and System II: Express Briefs, Jan. 2012. pdf

  • [J3] L. Xia, C. Hu, S. Redfield, S. Woracheewan, R. Khanna, J. Nejedlo, H. Liu, and P. Chiang, "Wireless Interconnects for Future Computing Systems," accepted, Intel Technology Journal, 2012. pdf

  • [C7] R. Khanna, D. Choudhury, P. Chiang, and H. Liu, "Innovative approach to server performance and power monitoring in data centers using wireless sensors (invited paper)," invited, IEEE Radio and Wireless Week, 2012. pdf

  • [C6] C. Hu, L. Xia, S. Redfield, S. Woracheewan, Rahul Khanna, Jay Nejedlo, Huaping Liu, and Patrick Chiang, "Design challenges for ultra-wideband communications within computer chassis," invited, IEEE International Symposium on Radio Frequency Integration, Beijing, China, Dec. 2011. pdf

  • [J2] L. Xia, H. Chen, Y. Huang, Z. Hong, and P. Y. Chiang, "100-Phase, Dual-Loop DLL for IR-UWB Coherent Receiver Synchronization", accepted, IET Circuits, Devices, and Systems, 2011. pdf

  • [J1] L. Xia, C. Hu, Y. Huang, Z. Hong, P. Y. Chiang, "Ultra-Wideband RF Transceiver Design in CMOS Technology," Chapter 3, Ultra Wideband Communications: Novel Trends / Book 3, InTech, 2011. pdf

  • [C5] S. Woracheewan, C. Hu, R. Khanna, J. Nejedlo, H. Liu, and P. Chiang, "Measurement and Characterization of Ultra-wideband Wireless Interconnects within Active Computing Systems", IEEE Symposium on VLSI-DAT, Hsinchu, Taiwan, April 2011. pdf

  • [C4] Karthik Jayaraman, Quadeer A. Khan, Baoyong Chi, and Patrick Y. Chiang, "Design and Analysis of 1-60GHz, RF CMOS Peak Detectors for LNA Calibration", IEEE International Symposium on VLSI Design, Automation, and Test, Taipei, Taiwan, April 2009. pdf

  • [C3] Changhui Hu, Steven Redfield, Huaping Liu, Rahul Khanna, Jay Nejedlo, and Patrick Chiang, "Transmitter Equalization for Multipath Interference Cancellation in Impulse Radio, Ultra-Wideband (IR-UWB) Transceivers", IEEE International Symposium on VLSI Design, Automation, and Test, Taipei, Taiwan, April 2009. pdf
  • [C2] Yike Cui, Baoyong Chi, Minjie Liu, Yulei Zhang, Yongming Li, Patrick Chiang, Zhihua Wang, "Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance," International Symposium on Circuits and Systems, New Orleans, May 2007. pdf

  • [C1] Patrick Chiang, William J. Dally, Ming-Ju E. Lee. Monolithic Chaotic Communications System. 2001 IEEE International Conference on Circuits and Systems, Sydney, Australia, May 6-9, 2001.

    (4) IOT Sensing

    A. Selected Publications

  • [C19] L. Shuo, et. al., "A 0.45V 687pW Low Noise Amplifier Front-End with 1.73 NEF for Energy-Scavenging IoT Sensors", accepted, IEEE International Wireless Symposium (IWS), 2016.

  • [C18] V. Behravan, S. Li, N. Glover, C.H. Chen, M. Shoaib, G. Temes, P.Y. Chiang, "A Compressed-Sensing Sensor-on-Chip Incorporating Statistics Collection to Improve Reconstruction Performance", accepted, CICC, 2015.

  • [C17] V. Behravan, M. Shoaib, P. Y. Chiang, "Rate-Adaptive Compressed-Sensing and Sparsity Variance of Biomedical Signals", accepted, Body Sensor Networks Conference, 2015.

  • [J6] C. H. Chen, et. al., "A micropower two-step incremental analog-to-digital converter", accepted, IEEE Journal of Solid-State Circuits, 2015.

  • [C16] C.H. Chen, Y. Zhang, T. He, P.Y. Chiang, and G.C. Temes, "A 11µW 250 Hz BW Two-Step Incremental ADC with 100 dB DR and 91 dB SNDR for Integrated Sensor Interfaces", accepted, CICC-2014. pdf
  • [C15] Rich Meier, Omri Almog, Nicholas Kelly, Patrick Chiang, "A Piezoelectric Energy-Harvesting Shoe System for Podiatric Sensing", accepted, EMBC-2014. pdf
  • [J5] L. Xia, J. Cheng, N. Glover, P. Chiang, "0.56 V, -20 dBm RF-Powered, Multi-Node Wireless Body Area Network System-on-a-Chip with Harvesting-Efficiency Tracking Loop", IEEE Journal of Solid-State Circuits, Feb. 2014. pdf
  • [C14] L. Wan, Y. Qin, P. Chiang, G. Chen, R. Liu, Z. Hong, "High-Sensitivity Photodetection Sensor Front-End, Detecting Organophosphourous Compounds for Food Safety," accepted, IEEE Custom Integrated Circuits Conference (CICC), 2013. pdf
  • [J4] C. Ma, C. Hu, J. Cheng, L. Xia, P. Y. Chiang, "A Near-Threshold, 0.16 nJ/b OOK-Transmitter with 0.18 nJ/b Noise-Cancelling Super-Regenerative Receiver for the Medical Implant Communications Service", Accepted, IEEE Transactions on Biomedical Circuits and Systems, 2013. pdf
  • [C13] X. Pu, L. Wan, Y. Sheng, P. Chiang, Y. Qin, and Z. Hong, "A Wireless 8-Channel ECG Biopotential Acquisition System for Dry Electrodes", IEEE Radio-Frequency Integration Technology Conference, Nov. 2012. pdf

  • [C12] Jiao Cheng, Lingli Xia, Chao Ma, Yong Lian, Xiaoyuan Xu, C. Patrick Yue, Zhiliang Hong, Patrick Y. Chiang, "A Near-Threshold, Multi-Node Wireless Body Area Network Sensor Powered by RF Energy Harvesting", IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, Sep. 2012. pdf (BEST POSTER AWARD).

  • [C11] B. Coker, J. Leung, A. Cohen, B. Goska, R. Albright, S. House, P. Chiang, "Wearable, Wireless Reflectance-Sensing Pulse Oximeter", accepted, IEEE Engineering in Medicine and Biology Conference (EMBC-2012), 2012. pdf

  • [C10] T. Morton, A. Weeks, S. Houses, P. Chiang, and C. Scaffidi, "Location and Activity Tracking with the Cloud", accepted, IEEE Engineering in Medicine and Biology Conference (EMBC-2012), 2012. pdf

  • [C9] Derek Chen, Joe Crop, Patrick Chiang, and Gabor Temes, "A 12-Bit 7uW/Channel 1 Khz/Channel Incremental ADC for Biosensor Interface Circuits", accepted, International Symposium on Circuits and Systems (ISCAS), May 2012. pdf

  • [C8] S. House, S. Connell, I. Miligan, D. Austin, T. Hayes, and P. Chiang, "Indoor Localization Using Pedestrian Dead Reckoning Updated with RFID-Based Fiducials", IEEE Engineering in Medicine and Biology Conference, Boston, MA, Aug. 2011. pdf

  • [C7] R. Albright, B. Goska, T. Hagen, M. Chi, G. Cauwenberghs, and P. Chiang, "OLAM: A Wearable, Non-Contact Sensor for Continuous Heart-Rate and Activity Monitoring", IEEE Engineering in Medicine and Biology Conference, Boston, MA, Aug. 2011. pdf

  • P. Chiang, "Wearable Sensor Electronics for Monitoring the Effects of Aging", (Invited workshop), IEEE Radio Frequency Integrated Circuits Sympoisum (RFIC), 2011.

  • [J3] L. Xia, S. Redfield, P. Chiang, "Experimental Characterization of an UWB channel for Body Area Networks", EURASIP Journal on Wireless Communcations and Networking, Jan. 2011. pdf

  • [J2] T. Lamers, P. Chiang, R. Ruby, B. Pruitt, "An Electrically-Addressable, Liquid Release Well Array for a Hand-held, Scent Dispense System", Micro/Nano Letters, Jan. 2011. pdf

  • [J1] B. Chi, J. Yao, P. Chiang, and Z. Wang, "A Fast-Settling, Wideband-IF, ASK Baseband Circuit for a Wireless Endoscope Capsule", IEEE Transactions on Circuits and Systems II: Express Briefs, April 2009. pdf

    B. Other Publications

  • [J1] W. Lei, et. al., "A Mobile-based High Sensitivity On-field Organophosphorus Compounds Detecting System for IoT-based Food Safety Tracking", accepted, Journal of Sensors, 2017.

  • [C20] Y. Zhao, et. al., "Improved Position Estimation by Fusing Multiple Inaccurate Inertial Measurement Unit Sensors", IEEE International Wireless Symposium (IWS), 2016.

  • [C20] H. Xu, et. al., "Method for Estimating the Distance Between Multiple IMU-Based Wearable Devices", accepted, IEEE International Wireless Symposium (IWS), 2016.

  • L. shuo, et. al., "A 20uW Dual-Channel Analog Front-End in 65nm CMOS for Portable ECG Monitoring System", accepted, IEEE Asicon, 2015.

  • Q. Yang, et. al., "Air-Kare: A Wi-Fi Based, Multi-Sensor, Real-Time Indoor Air Quality Monitor", accepted IEEE IWS Symposium, 2015.

  • [C6] S. Cahill-Weisser, R. Phillips, P. Chiang, and C. Scaffidi, "Cloud-Based Gait Speed and Variability Monitoring Using Smartphones", IEEE Healthcare Technology Conference: Translational Engineering in Health & Medicine, 2012. pdf

  • [C5] Y. Luo, C. Winstead, P. Chiang, "125Mbps Ultra-Wideband System Evaluation for Cortical Implant Devices", accepted, IEEE Engineering in Medicine and Biology Conference (EMBC-2012), 2012. pdf

  • [C4] S. D. Cahill-Weisser, B. Goska, R. Albright, S. Trost, and P. Chiang, "Comparison of the Accuracy Between the 'OLAM' Wearable Monitor and Commercial Devices," 2nd AMA-IEEE Medical Technology Conference: Healthcare IT, Boston, MA, Oct. 2011. pdf

  • [C3] Seungjin Baek, Ruiqing Ye, Charles Hu, Stephen Redfield, Huaping Liu, Tamara Hayes, and Patrick Chiang, "Preliminary Study of Indoor Ultrawideband Localization for At-Home Patient Monitoring", AMA-IEEE Medical Technology Conference on Individualized Healthcare, Washington DC, March 2010. pdf

  • [C2] R. Albright, B. Goska, P.Y. Chiang, "A Wireless Transceiver Platform for Comparing Various ISM Bands for Next-Generation Body Area Networks", AMA-IEEE Medical Technology Conference on Individualized Healthcare, Washington DC, March 2010. pdf

  • [C1] Ghionea, P. Dhagat, E. Chatterjee, V. Remcho, A. Jander, P. Chiang and J. Akse, "Lab On A chip Detection of Biomolecules Using Magnetic Bead Labels", presented at the 7th International Conference on Scientific and Clinical Applications of Magnetic Carriers, Vancouver, May 2008.
  • [P1] K. Lamers, P. Chaing, R. Flynn, Y-R. Rau, B. Pruitt, A. Ioakeimidi, "Electrically addressable liquid dispenser", US Patent #7715699, Issued May 11, 2010. pdf

    Feb-1-2013: 30 Journals; 54 Conference; 539 Citations on Google Scholar

    Feb-14-2014: 31 Journals; 64 Conference; 3 Patents; 738 Citations on Google Scholar

    Nov-10-2014: 35 Journals; 72 Conference; 4 Patents; 908 Citations on Google Scholar

    Dec-11-2015: 41 Journal; 76 Conference; 5 Patents; 1340 Citations on Google Scholar