2009

• Z. Feng, Y. Yi, Y. Zongren, P. Chiang, W. Hu, "A Low Latency Transceiver Macro with Robust Design Technique for Processor Interface", accepted, Asian Solid-State Circuits Conference, November 2009.
• T. Jiang and P. Chiang, "Design Techniques Enabling 10+ GSs, 6b, 100mW ADCs," Techcon 2009, Sep. 2009.
• T. Krishna, A. Kumar, J. Postman, M. Erez, P. Chiang, and L. Peh, "NOCHI: Network-on-Chip with Hybrid Interconnect", accepted, IEEE Micro, 2009.
• K. Hu, J. Hu, B. Otis, and P. Chiang, "A 1.6mW CMOS Injection-Locked Ring Oscillator with FBAR-Based PLL Reference," In submission, IEEE Microwave and Wireless Components Letters, 2009.
• B. Chi, J. Yao, P. Chiang, and Z. Wang, "A 0.18um CMOS GFSK Analog Front-End Using a Bessel-Based Quadrature Discriminator with On-Chip Automatic Tuning", accepted, IEEE Transactions on Circuits and Systems I: Regular Papers, 2009.
• B. Chi, J. Yao, P. Chiang, and Z. Wang, "A Fast-Settling, Wideband-IF, ASK Baseband Circuit for a Wireless Endoscope Capsule", accepted, IEEE Transactions on Circuits and Systems II: Express Briefs, 2009.
• K. Hu, T. Jiang, J.G. Wang, F. O'Mahony, and P. Chiang, "A 0.6mW/Gbps, 6.4-8.0Gbps Serial Link Receiver Using Local, Injection-Locked Ring Oscillators in 90nm CMOS", accepted, VLSI Circuits Symposium, June 2009.
• G. Zhuo, P. Chiang, and W. Hu, "A 10Gbps/ Wire-line Transceiver with Half Rate Period Calibration CDR", accepted,IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009.
• Tao Jiang and P. Chiang, "Sense Amplifier Power and Delay Characterization for Operation Under Low-Vdd and Low-Voltage Clock Swing", accepted to IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009.
• G. Zhuo, D. Kesharwani, P. Chiang, and W. Hu, "Measuring and Compensating for Process Mismatch Induced, Reference Spurs in Phase-Locked Loops Using a Sub-Sampled DSP", accepted to IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009.
• Kang-Min Hu and P. Chiang, "Comparison of on-Die Global Clock Distribution Methods for Parellel Serial Links", accepted to IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009.
• Karthik Jayaraman, Quadeer A. Khan, Baoyong Chi, and Patrick Y. Chiang, "Design and Analysis of 1-60GHz, RF CMOS Peak Detectors for LNA Calibration", to appear in IEEE International Symposium on VLSI Design, Automation, and Test, Taipei, Taiwan, April 2009.
• Changhui Hu, Steven Redfield, Huaping Liu, Rahul Khanna, Jay Nejedlo, and Patrick Chiang, "Transmitter Equalization for Multipath Interference Cancellation in Impulse Radio, Ultra-Wideband (IR-UWB) Transceivers", to appear in IEEE International Symposium on VLSI Design, Automation, and Test, Taipei, Taiwan, April 2009.

2008

• Tushar Krishna, Amit Kumar, Patrick Chiang, Mattan Erez and Li-Shiuan Peh, " NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication " Proceedings of Hot Interconnects (HOTI), Stanford, California, August 2008.
• Ghionea, P. Dhagat, E. Chatterjee, V. Remcho, A. Jander, P. Chiang and J. Akse, "Lab On A chip Detection of Biomolecules Using Magnetic Bead Labels", presented at the 7th International Conference on Scientific and Clinical Applications of Magnetic Carriers, Vancouver, May 2008.

2007

• Yike Cui, Baoyong Chi, Minjie Liu, Yulei Zhang, Yongming Li, Patrick Chiang, Zhihua Wang. Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance. International Symposium on Circuits and Systems, New Orleans, May 2007.

Before Oregon State

2006

2005

• Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer. IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, April 2005, pp. 1004-1011.

2004

• Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer. 2004 Symposium on VLSI Circuits, June 15-19, 2004, pp. 272-275.

2002

• Patrick Chiang, William J. Dally, Ming-Ju E. Lee. A 20Gb/s 0.13um CMOS Serial Link, Hotchips 2002, Stanford, CA, Aug. 18-20, 2002.

2001

• Patrick Chiang, William J. Dally, Ming-Ju E. Lee. Monolithic Chaotic Communications System. 2001 IEEE International Conference on Circuits and Systems, Sydney, Australia, May 6-9, 2001.
• Ming-Ju E. Lee, William Dally, Patrick Chiang. Low-Power Area-Efficient High-Speed I/O Circuit Techniques. IEEE Journal of Solid-State Circuits, November 2000, Vol. 35, No. 11, pp. 1591-1599.
• Ming-Ju E. Lee, William Dally, Patrick Chiang. A 90mW 4Gb/s Equalized I/O Circuit with Input Offset Cancellation. International Solid State Circuits Conference, San Francisco, February 2000, TP 15.3, pp. 252-253.

2000

• Ming-Ju E. Lee, William Dally, Patrick Chiang. Low-Power Area-Efficient High-Speed I/O Circuit Techniques. IEEE Journal of Solid-State Circuits, November 2000, Vol. 35, No. 11, pp. 1591-1599.
• Ming-Ju E. Lee, William Dally, Patrick Chiang. A 90mW 4Gb/s Equalized I/O Circuit with Input Offset Cancellation. International Solid State Circuits Conference, San Francisco, February 2000, TP 15.3, pp. 252-253.

1999

• Cormac Conroy, Samuel Sheng, Arnold Feldman, Greg Uehara, Albert Yeung, Chih-Jen Hung, Vivek Subramanian, Patrick Chiang, Paul Lai, Xiaomin Si, Jerry Fan, David Flynn, Meiqing He. A CMOS Analog Front-End IC for DMT ADSL. International Solid State Circuits Conference, San Francisco, February 1999, pp. 240-241.