ECE 272- Digital Logic Design Laboratory
Catalog Description: Laboratory to accompany ECE 271, Digital Logic
Design. This course illustrates topics covered in the lectures of ECE 271 using
computer-aided design and verification tools and breadboards.
Prerequisites:
By course: ENGR 201; COREQ: ECE 271.
By topic: Previous exposure to laboratory procedures, Basic notion of Windows
Operating System.
Courses that require this as a prerequisite: none
Credits: 1 Terms Offered: Spring annually
Instructors:
Primary: A. Tenca
Secondary: C. Koç
Textbook: NONE
Course Learning Objectives:
Students must demostrate the ability to:
- Design combinational and sequential system using integrated circuits available
in the market (FPGA chips are presently being used). (ABET Outcomes: a,c,k)
- Implement and test the designed circuits using laboratory equipment that
already provides the power supply, binary switches, and LED outputs. (ABET
Outcomes: a,c,k)
- Develop a small project, which usually consists in the design of a digital
controller. The controller specification is provided in text form, and the
students are exposed to all design phases: formal specification, design of
gate networks, implementation, and test. (ABET Outcomes: a,b,c,e,k)
- Report the development of the experiments and laboratory results in written
form (laboratory reports). (ABET Outcome: g)
Topics:
- Lab 1: Introduction to laboratory procedures and development system (Xilinx
tools and Digilent board)
- Lab 2: Logic Gates, 2-Level Gate Networks and Switching (Boolean) Algebra
- Lab 3: Combinational Circuit Design and Standard Combinational Modules
- Lab 4: Latches and Flip Flops
- Lab 5: Sequential System Analysis and Design
- Lab 6: Counters and Registers
- Lab 7: Project - design of a control system
Structure:
One 170-minute laboratory section per week.
Students must study and prepare the experiments before coming to the lab sections,
and prepare a report on their work due one week after the section when they
completed their lab section.
Original: 4/01
Revised: