July 2017
ELECTRICAL & COMPUTER ENGINEERING
OREGON STATE UNIVERSITY
College of Engineering
TEMES, Gabor C.
Professor
DEGREES
 Dipl. Ing. (B.S.), Electrical Engineering, Technical University of Budapest, 1952
 Dipl. Phys. (B.S.), Physics, Eotvos University, 1955
 Ph.D., Electrical Engineering, University of Ottawa, 1961
 D.Eng. (honorary), Technical University of Budapest, 1991
ACADEMIC POSITIONS
 Lecturer, Technical University of Budapest, October 1951October 1952
 Assistant Professor, Technical University of Budapest, October 1952November 1956
 Lecturer, Sherbrooke University, Canada, January 1957May 1957
 Lecturer, University of Ottawa, October 1961April 1964
 Lecturer, University of Santa Clara, May 1966September 1969
 Lecturer, Stanford University, September 1966June 1966
 Professor, Department of Electrical Engineering, University of California, 19701990; Department Chair, 19751979
 Visiting Professor, Technical University of Munich, July 1979August 1979
 Professeur Invite, Ecole Polytechnique Federale de Lausanne, April 1985August 1985
 Professor, Department of Electrical and Computer Engineering, Oregon State University, 1990present; Department Head, 19901994
NONACADEMIC POSITIONS
 Project Engineer, Measurement Engineering Ltd., June 1957April 1959
 Laboratory Supervisor, Northern Electric R & D Labs, April 1959April 1964
 Research Group Leader, Stanford University, April 1964April 1966
 Corporate Consultant, Ampex Corporation, April 1966August 1969
Consultant to:


 Xerox Corp. Microelectronics, Redondo Beach, CA, 19801987
 AEG Telefunken Backnang, West Germany, 19801987
 Hughes Research Labs, Malibu, CA, 19871990, 2008present
 Tektronix, Beaverton, OR, 19911992
 Microchip, Switzerland, 20022004
 Cypress Semiconductor, 20062009
 EGI Inc., 20062009
FIELDS OF SPECIALIZATION
 Data Converters
 SwitchedCapacitor Circuits
 Analog and Digital Signal Processing
PROFESSIONAL ACTIVITIES
Professional Societies
Institute of Electrical and Electronics Engineers (IEEE)



 IEEE Circuits and Systems Society (CAS)
Professional Recognition



 Darlington Award of the IEEE CAS Society (with H.J. Orchard), 1969
 Fellow of IEEE, 1972
 Darlington Award of the IEEE CAS Society (with M.S. Lee, C. Chang, and M. Ghaderi), 1981
 Outstanding Engineer Merit Award of IAE, 1981
 Western Electric Fund Award of ASEE, 1982
 IEEE Centennial Medal, 1984
 Andrew Chi Prize of IEEE I&M Society, 1985
 Education Award, IEEE CAS Society, 1987
 Distinguished Professor, 19881990; Distinguished Emeritus Professor, 1990 , UCLA
 Technical Achievement Award, IEEE CAS Society, 1989
 Honorary Doctorate, Technical University of Budapest, 1991
 Senior Research Award, Humboldt Foundation, Germany, 1991
 Distinguished Lecturer, IEEECAS, 19911992
 Best Evening Panel Award, 1996 International SolidState Circuits Conference, February 1996
 IEEE Graduate Teaching Award, 1998
 Member, Review Team to evaluate the ECE Department at the University of Toronto, May 1999
 Keynote Speaker, 42nd IEEE Midwest Symposium on Circuits and Systems, August 1999
 IEEE Circuits and Systems Society Golden Jubilee Medal, 1999
 IEEE Third Millennium Medal, 2000
 CDADIC Best Project Award, February 2001
 Plenary Speaker, VII Iberchip Workshop, Montevideo, Uruguay, March 2001
 IEEE CAS Society Distinguished Lecturer, 2001/2
 Distinguished Lecturer, University of Toronto, 2004
 Invited Speaker, U.C. Berkeley IC Seminar Oct. 4, 2005
 Distinguished Lecturer, UCLA, Jan. 23, 2006
 IEEE Gustav Robert Kirchhoff Award, Feb. 2006
 IEEE CAS Mac Van Valkenburg Award, May 2009
 OSU COE Research Award, Sept. 2010
 “Gabor Temes: Creativity in Analog Circuits,” Special Issue of the IEEE SolidState Circuits Magazine, vol. 5, No. 2, Spring 2013.
 National Academy of Engineering, Febr. 2015
 2017 SIASRC University Researcher Award
Committees, Commissions and Boards
Institute of Electrical and Electronics Engineers
Circuits and Systems Society



 Chair, Technical Program Committee, Symposium on Circuits and Systems, 1970
 Administrative Committee, 19731974
 Best Paper Award Committee Chairman, 19741975
 Fellow Award Committee, 19741980
 Nominations Committee Chairman, 19781979
 Awards Committee, 19851988, 19981999
 Service Award Committee Chairman, 19861987
 Teaching Award Committee Chairman, 19871993
 Vice President, 19671969, 19711972
 Valkenburg Award Committee Chairman, 19981999, 20092010
 Fellow Award Committee, 2001
 Technical Achievement Award Committee, 20022003, 20092010
 Teaching Award Committee, 20052008
 Gustav Robert Kirchhoff Award Committee, 20062008
 Vitold Belevitch Award Committee Chairman 2013
 Vitold Belevitch Award Committee, 20082009
 Charles Desoer Research Award Committee, 20142015
 CAS John Choma Education Award Committee, 20162017
Education Group



 Fellow Award Committee, 19761978
IEEE Transactions on Circuit Theory



 Guest Editor, Special Issue on Modern Filter Design, 1968
 Associate Editor, 19671969
 Editor, 19691971
Journal of the Franklin Institute



 Member of the Board of Associate Editors, 19711973
IEEE Trans. on Circuits and Systems and IEEE Trans. on Communications
Proceedings of the IEEE



 Guest Editor, 1983
 Member of Editorial Board, 19891994
Circuits, Systems and Signal Processing



 Associate Editor, 19841989
Analog Integrated Circuits and Signal Processing, Kluwer



 Associate Editor, 1992present
Advisory Committee, Ph.D. Program, Polytechnic, Institute of Turin, Italy, 19811982
Scientific Advisory Board, Information Technology Research Centre (University of Toronto), 19891991
International Expert Commission, National Center for Microelectronics, Spain, 19901991
PUBLICATIONS
Books, Chapters in Books, and Editorships
 Temes, G.C., Electronphysics, Technical University Press, Budapest, 1953.
 Berkes, T. and Temes, G.C., Nuclear Physics Measurements, Technical University Press, Budapest, 1956.
 Temes, G.C. and Kalman, G., Selected Problems in Electronphysics, Technical University Press, Budapest, 1956.
 Temes, G.C., “Interaction Between the EnergyLosses of Protons in Free Electron Gas,” KFKI Kozlemenyek, Proc. of the Central Research Inst. of Physics, Budapest, 1957, 5:7783.
 Temes, G.C., Boire, P., and Banfill, H., “A New Brightness Meter,” Proc. of the Instrument Soc. of America, June 1960, pp. 61 to 68.
 Temes, G.C., “Optimization Methods in Circuit Design,” and “Filter Design in Transformed Frequency Variable,” Chapters 5 and 6 in Computer Oriented Circuit Design, F.F. Kuo and W.C. Magnuson, eds., PrenticeHall, pp. 191303, October 1969.
 Smith, B.R. and Temes, G.C., “An Iterative Approximation Procedure for Automatic Filter Synthesis,” in ComputerAided Filter Design, G. Szentirmai , ed., IEEE Press, New York, pp. 1116, 1973.
 Temes, G.C. and Gyi, M., “Design of Filters with Arbitrary Passband and Chebyshev Stopband Attenuation,” in ComputerAided Filter Design, G. Szentirmai, ed., IEEE Press, New York, pp. 2021, 1973.
 Orchard, H.J. and Temes, G.C., “Filter Design Using Transformed Variables,” in ComputerAided Filter Design, G. Szentirmai, ed., IEEE Press, New York, pp. 90113, 1973.
 Temes, G.C. and Calahan, D.A., “ComputerAided Network OptimizationThe State of the Art,” in ComputerAided Filter Design, G. Szentirmai, ed., IEEE Press, New York, pp. 187218, 1973.
 Temes, G.C. and Zai, DY.F., “Least pth Approximation,” in ComputerAided Filter Design, G. Szentirmai, ed., IEEE Press, New York, pp. 219221, 1973.
 MacDonald, J.D. and Temes, G.C., “A Simple Method for the Predistortion of Filter Transfer Functions,” in ComputerAided Filter Design, G. Szentirmai, ed., IEEE Press, New York, pp. 248251, 1973.
 Smith, B.R. and Temes, G.C., “An Iterative Approximation Procedure for Automatic Filter Synthesis,” in ComputerAided Circuit Design Simulation and Optimization, S.W. Director, ed., Dowden, Hutchingson & Ross, Inc., Stroudsburg, PA, pp. 226231, 1973.
 Temes, G.C. and Mitra, S.K., eds., Modern Filter Theory and Design, Wiley, New York, November 1973.
 Temes, G.C. and Mitra, S.K., eds., Modern Filter Theory and Design, Russian Translation, MIR Publishing Co., Moscow, 1977; also translated into Polish.
 Temes, G.C. and La Patra, J.W., Introduction to Circuit Synthesis and Design, McGrawHill, New York, 1977; Far East Edition, 1980.
 Temes, G.C., Orchard, H.J., and Jahanbegloo, M., “SwitchedCapacitor Filter Design Using the Bilinear zTransform,” in Analog MOS Integrated Circuits, P.R. Gray, D.A. Hodges, and R.W. Brodersen, eds., IEEE Press, New York, pp. 275280, 1980.
 Temes, G.C., Orchard, H.J., and Jahanbegloo, M., “SwitchedCapacitor Filter Design Using the Bilinear zTransform,” in Modern Active Filter Design, R. Schaumann, M.A. Soderstrand, and K.R. Laker, eds., IEEE Press, New York, pp. 318323, 1981.
 Gregorian, R., Martin, K.W., and Temes, G.C., “SwitchedCapacitor Circuit Design,” in MOS SwitchedCapacitor Filters, G. Moschytz, ed., IEEE Press, New York, pp. 180205, 1984.
 Lee, M.S., Temes, G.C., Chang, C., and Ghaderi, B., “Bilinear SwitchedCapacitor Ladder Filter,” in MOS SwitchedCapacitor Filters, G. Moschytz, ed., IEEE Press, New York, pp. 325335, 1984.
 Temes, G.C., Orchard, H., and Jahanbegloo, M., “SwitchedCapacitor Filter Design Using the Bilinear zTransform,” in MOS SwitchedCapacitor Filters, G. Moschytz, ed., IEEE Press, New York, pp. 319324, 1984.
 Gregorian, R. and Temes, G.C., Analog MOS Integrated Circuits for Signal Processing, Wiley, New York, 1986.
 Temes, G.C., ed., Integrated Analog Filters, IEEE Press, New York, 1988.
 Gregorian, R. and Temes, G.C., “SwitchedCapacitor Filters: Circuits and Applications,” Chapter 5 in Miniaturized and Integrated Filters, Wiley, New York, NY, pp. 159219, 1989.
 Candy, J.C. and Temes, G.C., eds., Oversampling DeltaSigma Data Converters, IEEE Press, New York, NY, 1991. Also coauthor of the introductory paper of the book.
 Larson, L.E. and Temes, G.C., “Signal Conditioning and Interface Circuits,” Chapter 10 in Digital Signal Processing Handbook, Wiley, New York, NY, pp. 677720, 1993.
 Temes, G.C., “DeltaSigma Data Converters,” Chapter 10 in Design of AnalogDigital VLSI Circuits for Telecommunications and Signal Processing, J. Franca and Y. Tsividis, eds., PrenticeHall, Englewood Cliffs, NJ, pp. 317340, 1994.
 Temes, G.C., “DeltaSigma D/A Converters,” Chapter 4.2 in Circuits and Systems Tutorials, Ch. Toumazou, ed., IEEE, 1994, pp. 224234.
 Norsworthy, S., Schreier, R., and Temes, G.C., eds., DeltaSigma Data Converters, IEEE Press, New York, NY, 1996. Also, coauthor of Chapters 8 and 10.
 Temes, G., “Autozeroing and Correlated Doubling Sampling,” in Analog Circuit Design, J. Huising, R. van de Plassche, and W. Sansen, eds., Kluwer, Dordrecht, Netherlands, pp. 4564, 1996.
 Schreier, R., Steensgaard, J., and Temes, G., “Speed vs. Dynamic Range TradeOff in Oversampling Data Converters,” Chapter 21 in: TradeOffs in Analog Integrated Circuits, B. Gilbert, G. Moschytz, and Ch. Toumazou, eds., Wiley, 2002.
 Schreier, R. and Temes, G.C., Understanding DeltaSigma Data Converters, IEEE Press/Wiley Interscience, 2005. Japanese translation, 2007, published by Maruzen Co.; Chinese ed. by Sciencep, 2007 (?).
 Lee, K. and Temes, G.C., “NoiseCoupled DeltaSigma ADCs, in Analog Circuit Design, Springer, 2011.
 Temes, G.C., “Incremental and ExtendedRange Data Converters,” in Design, Modeling and Testing of Data Converters, Springer, 2013.
 Chen, CH, He, T. and Temes, G.C. “Micropower incremental ADCs,” in Analog Circuit Design, Springer, 2015.
 Temes, G.C. “DeltaSigma Data Converters,” in A Brief History of Circuits and Systems, IEEE, 2016.
 Pavan, S., Schreier, R. and Temes, G.C., Understanding DeltaSigma Data Converters, second edition, IEEE Press/Wiley Interscience, 2017.
Technical Journals
 Temes, G.C., “IntegratorType Frequency Dividers and Counters,” Hiradastechnika, Budapest, 1954.
 Fodor, G. and Temes, G.C., “Analog Computing Circuits,” Meres es Automatika, Budapest, 1955.
 Fodor, G. and Temes, G.C., “Differentiating Networks,” Hiradastechnika, Budapest, 1955.
 Fodor, G. and Temes, G.C., “Differentiating and Integrating Networks,” Acta Technica Hungarica, 16:73104, Budapest, 1957 (in English).
 Temes, G.C., “Interaction Between the EnergyLosses of Protons in Free Electron Gas,” KFKI Kozlemenyek, Proc. of the Central Research Inst. of Physics, Budapest, 1957, 5:7783.
 Temes, G.C., Boire, P., and Banfill, H., “A New Brightness Meter,” Proc. of the Instrument Soc. of America, June 1960, pp. 61 to 68.
 Temes, G.C., “The Synthesis of General Parameter Filters,” Communications & Electronics, 8054:181186, May 1961.
 Schwelb, O. and Temes, G.C., “The Design of ThermistorResistor Temperature Sensing Devices,” ElectroTechnology, 68(5):7175, November 1961.
 Temes, G.C., “An Additional Extension of a Network Theorem,” Inst. of Radio Engineers Trans. on Circuit Theory, 8:488489, December 1961.
 Temes, G.C., “Optimal Selectivity of Harmonic Suppressing Filter Sets,” Inst. of Radio Engineers Trans. on Circuit Theory, 9(2):187188, June 1962.
 Temes, G.C., “FirstOrder Estimation and Precorrection of Parasitic Effects in Filters,” Inst. of Radio Engineers Trans. on Circuit Theory, 9:385399, December 1962.
 Temes, G.C. and Saal, R., “Comments on the Design of Filters by Synthesis,” Inst. of Radio Engineers Trans. on Circuit Theory, 9:409410, December 1962.
 Mac Donald, J.D. and Temes, G.C., “A Simple Method for the Predistortion of Filter Transfer Functions,” Inst. of Radio Engineers Trans. on Circuit Theory, 10:447450, September 1963.
 Temes, G.C., “The Synthesis of Filters with Maximally Flat Passband and Arbitrary Stopband Attenuation,” Canadian Electronics Engineering, 8:2933, February 1964.
 Smith, B.R. and Temes, G.C., “An Iterative Approximation Procedure for Automatic Filter Synthesis,” IEEE Trans. on Circuit Theory, 12:107112, March 1965.
 Christian, E. and Temes, G.C., “On the Szentirmai Transformation,” IEEE Trans. on Circuit Theory, 13:450452, December 1966.
 Temes, G.C. and Bingham, J.A.C., “Iterative Chebyshev Approximation for Network Synthesis,” IEEE Trans. on Circuit Theory, 14:3137, March 1967.
 Szego, P., Temes, G.C., and Orchard, H.J., “Optimum BandLimited System with Monotonic Step Response,” Proc. of the IEEE, 55:698700, May 1967.
 Temes, G.C. and Calahan, D.A., “ComputerAided Network Optimization  the State of the Art,” Proc. of the IEEE, 55:18321863, November 1967.
 Temes, G.C. and Orchard, H.J., “Maximally Flat Approximation Techniques,” Proc. of IEEE, 56:6566, January 1968.
 Orchard, H.J. and Temes, G.C., “Filter Design Using Transformed Variables,” IEEE Trans. on Circuit Theory, 15:486508, New York, December 1968.
 Temes, G.C., “The Present and Future of Filter Theory,” IEEE Trans. on Circuit Theory, 15:302, December 1968.
 Temes, G.C., “ComputerAided Electrical Circuit Design,” Readout, 8(2):1415, February 1969.
 Temes, G.C. and Zai, D., “Least pth Approximation,” IEEE Trans. on Circuit Theory, 16:235237, May 1969.
 Temes, G.C., “A Physical Proof of Tellegen’s Theorem,” Proc. of the IEEE, 57(6):11831184, June 1969.
 Temes, G.C., “Exact Computation of the Group Delay and its Sensitivities Using the Adjoint Network Concept,” Electronic Letters, 6(15):483485, July 23, 1970.
 Temes, G.C., “Circuit Theory of the 1970's,” IEEE Trans. on Circuit Theory, 17:468, November 1970.
 Temes, G.C. and Gadenz, R.N., “Simple Technique for the Prediction of DissipationInduced Loss Distortion,” Electronic Letters, 6:836837, December 1970.
 Gadenz, R.N. and Temes, G.C., “Computation of DissipationInduced Loss Distortion in LumpedDistributed Networks,” Electronic Letters, 7:10, May 1971.
 Gadenz, R.N. and Temes, G.C., “An Efficient Procedure for the Statistical Transient Analysis of Switching Circuits,” ComputerAided Design, 3(4):1925, Summer 1971.
 Hayes, L.L. and Temes, G.C., “An Efficient Numerical Method for the Computation of Zeroand PoleSensitivities,” Int. J. of Electronics, 1(11):2131, 1972.
 Temes, G.C., “The Prolate Filter: An Ideal Lowpass Filter with Optimum StepResponse,” J. of the Franklin Inst., 293:77103, February 1972.
 Temes, G.C., “Effects of Semiuniform Losses in Reactance TwoPorts,” Electronic Letters, 8:161163, March 1972.
 Temes, G.C., Ebers, R.M., and Gadenz, R.N., “Some Novel Applications of the Adjoint Network Concept in FrequencyDomain Circuit Analysis and Optimization,” ComputerAided Design, 4:129134, April 1972.
 Temes, G.C. and Barcilon, F., “A Lower Bound for the Minimum Risetime of Bandlimited Systems,” IEEE Trans. on Circuit Theory, CT19:280282, May 1972.
 Temes, G.C., Kurtz, J., and Orchard, H.J., “Least Squares Passband Filters,” IEEE Trans. on Circuit Theory, CT19:302304, May 1972.
 Gadenz, R.N. and Temes, G.C., “A Computational Algorithm for the Design of Elliptic Filters,” Electronics Letters, 8:323324, June 29, 1972.
 Barcilon, V. and Temes, G.C., “Optimum Impulse Response and the van der Maas Function,” IEEE Trans. on Circuit Theory, CT19:336342, July 1972.
 Temes, G.C., “Design Formulas for Cascaded TwoPorts,” IEEE Trans. on Circuit Theory, CT19:528530, September 1972.
 Gadenz, R.N. and Temes, G.C., “Efficient Hybrid and StateSpace Analysis of the Adjoint Network,” IEEE Trans. on Circuit Theory, CT19:520521, September 1972.
 Temes, G.C., Barcilon, V., and Marshall, F., “The Optimization of Bandlimited Systems,” Proc. of the IEEE, 61:196234, February 1973 (invited).
 Marshall, F.C. and Temes, G.C., “Generalized Linear Minimax Approximation of System Functions with Constraints,” IEEE Trans. on Circuit Theory, CT20:429432, July 1973.
 Temes, G.C. and Orchard, H.J., “FirstOrder Sensitivity and WorstCase Analysis of Doubly Terminated Reactance Twoports,” IEEE Trans. on Circuit Theory, CT20:567571, September 1973.
 Gadenz, R.N. and Temes, G.C., “Iterative Compensation Techniques for Lossy or Mismatched Twoports,” IEEE Trans. on Circuit Theory, CT20:599603, September 1973.
 Breen, R.H. Jr. and Temes, G.C., “Applications of Golub's Algorithm in Circuit Optimization and Analysis,” IEEE Trans. on Circuit Theory, Special Issue on ComputerAided Design, CT20:687690, November 1973.
 Gadenz, R.N., RezaiFakhr, G., and Temes, G.C., “A Method for the Fast Computation of Large Tolerance Effects,” IEEE Trans. on Circuit Theory, Special Issue on ComputerAided Design, CT20:704708, November 1973.
 Orchard, H.J. and Temes, G.C., “A Design Technique for Vestigial Sideband Filters,” IEEE Trans. Circuits & Systems, CAS21:532540, July 1974.
 Willson, A.N. Jr., Temes, G.C., and Gadenz, R.N., “On the Active Realization of Lossless TwoPorts,” IEEE Trans. on Circuit Theory, pp. 6365, January 1975.
 RezaiFakhr, M.G. and Temes, G.C., “Statistical LargeTolerance Analysis on Nonlinear Circuits in the Time Domain,” IEEE Trans. on Circuit Theory, pp. 1521, January 1975.
 RezaiFakhr, M.G. and Temes, G.C., “Node Elimination in Linear Active Circuits,” Electronic Letters, 11:121122, March 20, 1975.
 Marshall, F.C. and Temes, G.C., “Binary Windows for the Discrete Fourier Transform,” Proc. of the IEEE, pp. 13701371, September 1975.
 Temes, G.C., “Multiple Fault Simulation in Linear Active Circuits,” Electronics Letters, 12:467468, September 2, 1976.
 Babic, H. and Temes, G.C., “Optimum LowOrder Windows for Discrete Fourier Transform Systems,” IEEE Trans. on Acoustics, Speech & Signal Processing, ASSP24:512517, December 1976.
 Temes, G.C., “WorstCase Error Analysis for the Fast Fourier Transform,” Electronic Circuits and Systems, 1(3):110116, April 1977.
 Temes, G.C., “The Past and Present of Circuit Theory and the CAS Transactions,” IEEE Trans. on Circuits and Systems, CAS24:671672, December 1977.
 Temes, G.C. and Cho, K.M., “LargeChange Sensitivity of Linear Digital Networks,” IEEE Trans. on Circuits and Systems, CAS25(2):113114, February 1978.
 Temes, G.C., “Graduate Education for Electrical Engineers at UCLA,” Creative Science & Technology, pp. 2224, FebruaryMarch 1978.
 Temes, G.C. and Young, I.A., “An Improved SwitchedCapacitor Integrator,” Electronics Letters, 14(9):287288, April 1978.
 Temes, G.C., “The Derivation of SwitchedCapacitor Filters from ActiveRC Prototype,” Electronics Letters, 14(12):361362, June 1978.
 Gregorian, R. and Temes, G.C., “Design Techniques for Digital and Analog AllPass Circuits,” IEEE Trans. on Circuits & Systems, CAS25(12), 981988, December 1978.
 Temes, G.C., Orchard, H.J., and Jahanbegloo, M., “SwitchedCapacitor Filter Design Using the Bilinear zTransform,” IEEE Trans. on Circuits and Systems, CAS25(12):10391044, December 1978.
 Temes, G.C. and Jahanbegloo, M., “SwitchedCapacitor Circuits Which Are Bilinearly Equivalent to a Floating Inductor or FDNR,” Electronics Letters, 5(3):8788, February 1, 1979.
 Temes, G.C., Invited Comments, Special Issue on Curriculum Development, IEEE Trans. on Education, p. 42, May 1979.
 Gregorian, R. and Temes, G.C., “SelfEqualizing SampleandHold Circuits,” Electronics Letters, 15(13):367368, June 1979.
 Temes, G.C. and Gregorian, R., “Compensation for Parasitic Capacitances in SwitchedCapacitor Filters,” Electronics Letters, 15(13):377379, June 1979.
 Nossek, J.A. and Temes, G.C., “Entwurf von SchalterKondensatorFiltern mit Hilfe der Bilinearen Transformation,” ("SwitchedCapacitor Filter Design with the Aid of the Bilinear Transformation"), Archiv fur Elektornik und Ubertragungstechnik, 34(3):118124, March 1980.
 Orchard, H.J. and Temes, G.C., “Spectral Analysis of SwitchedCapacitor Filters Designed Using the Bilinear zTransform,” IEEE Trans. on Circuits and Systems, CAS27:185190, March 1980.
 Temes, G.C. and Ghaderi, M.B., “Bilinear SwitchedCapacitor Ladder Filter with Reduced Number of Amplifiers,” Electronics Letters, 16:412414, May 22, 1980.
 Temes, G.C., “Finite Amplifiers Gain and Bandwidth Effects in SwitchedCapacitor Filters,” IEEE J. of SolidState Circuits, SC15:358361, June 1980.
 Nossek, J. and Temes, G.C., “SwitchedCapacitor Filter Design Using Bilinear Element Modeling,” IEEE Trans. on Circuits and Systems, Special Issue on Integrated Filters for Telecommunication, CAS27:481491, June 1980.
 Szentirmai, G. and Temes, G.C., “SwitchedCapacitor Building Blocks,” IEEE Trans. on Circuits and Systems, Special Issue on Integrated Filters for Telecommunication, CAS27:492501, June 1980.
 Muller, G. and Temes, G.C., “A Simple Method for Analysis of a Class of SwitchedCapacitor Filters,” Electronics Letters, 16(2):852853, October 23, 1980.
 Gregorian, R., Nicholson, E., and Temes, G.C., “Integrated Bandsplit Filter System for a DualToneMultifrequency Receiver,” Microelectronics Journal, 11(6):512, November/December 1980.
 Lee, M.S. Temes, G.C., Chang, C., and Ghaderi, M.B., “Bilinear SwitchedCapacitor Ladder Filters,” IEEE Trans. on Circuits and Systems, CAS28:811822, August 1981.
 Ghaderi, M.B., Temes, G.C., and Law, S., “Linear Interpolation Using CCD’s or SwitchedCapacitor Filters,” IEEE Proc., Part G, Electronic Circuits and Systems, pp. 213215, August 1981 (invited paper).
 Muller, G. and Temes, G.C., “A Pauper’s Algorithm for SwitchedCapacitor Circuit Analysis,” Electronics Letters, 17:942944, December 1981.
 Ghaderi, M.B., Nossek, J.A., and Temes, G.C., “NarrowBand SwitchedCapacitor Bandpass Filters,” IEEE Trans. on Circuits and Systems, CAS29:557571, August 1982.
 Shyu, J.B., Temes, G.C., and Yao, K., “Random Errors in MOS Capacitors,” IEEE Journal of SolidState Circuits, SC17:10701076, December 1982.
 Watanabe, K. and Temes, G.C., “A SwitchedCapacitor Digital Multiplier,” Electronic Letters, 19:3334, January 1983.
 Hsu, T.H. and Temes, G.C., “Improved Input Stage for Bilinear SwitchedCapacitor Ladder Filters,” IEEE Trans. on Circuits and Systems, CAS30:758760, October 1983.
 Orchard, H.J. and Temes, G.C., “General Sensitivity Formulas for Lossless TwoPorts,” Electronics Letters, 19:576578, July 1983.
 Gregorian, R., Martin, K.W., and Temes, G.C., “SwitchedCapacitor Circuit Design,” Proceedings of the IEEE, 71:941966, August 1983.
 Rodriguez, B.A., Temes, G.C., et al., “An NMOS Buffer Amplifier,” IEEE Trans. on Electron Devices, Special Corresp., ED31:203205, February 1984.
 Temes, G.C. and Haug, K., “Improved OffsetCompensation Schemes for SwitchedCapacitor Circuits,” Electronics Letters, 20:508509, June 1984.
 Watanabe, K. and Temes, G.C., “A SwitchedCapacitor Multiplier/Divider with digital and Analog Outputs,” IEEE Trans. on Circuits and Systems, CAS31:796800, September 1984.
 Babanezhad, J.N. and Temes, G.C., “A Linear NMOS Depletion Resistor and its Application in an Integrated Amplifier,” IEEE J. of SolidState Circuits, SC19:932938, December 1984.
 Watanabe, K. and Temes, G.C., “A SwitchedCapacitor Digital Capacitance Bridge,” IEEE Trans. on Instrumentation and Measurements, IM33:247251, December 1984.
 Shyu, J.B., Temes, G.C. and Krumennacher, F., “Random Error Effects in Matched MOS Capacitors and Current Sources,” IEEE J. of SolidState Circuits, SC19:948955, December 1984.
 Shum, D.K. and Temes, G.C., “StrayInsensitive Differential Input Stages for A/D Convertors,” Electronics Letters, 20:10411042, December 1984.
 Orchard, H.J., Temes, G.C., and Cataltepe, T., “Sensitivity Formulas for Terminated Lossless TwoPorts,” IEEE Trans. on Circuits and Systems, CAS32: 459466, May 1985.
 Temes, G.C., “HighAccuracy Pipeline A/D Convertor Configuration,” Electronics Letters, 21: 762763, August 1985.
 Robert, J., Temes, G.C., Krummenacher, I., Valencic, V., and Deval, P., “Offset and ClockFeedthrough Compensated SwitchedCapacitor Integrators,” Electronics Letters, 21: 941942, September 1985.
 Hsu, T.H. and Temes, G.C., “An Improved Circuit for PseudoNPath SwitchedCapacitor Filters,” IEEE Trans. on Circuits and Systems, CAS32: 10711073, October 1985.
 Haug, K., Maloberti, F., Temes, G.C., “SwitchedCapacitor Integrators with Low FiniteGain Sensitivity,” Electronics Letters, 21: 11561157, November 1985.
 Babanezhad, J.N. and Temes, G.C., “A 20V Four Quadrant CMOS Analog Multiplier,” IEEE J. of SolidState Circuits, SC20: 11581168, December 1985.
 Temes, G.C., “The Compensation of Amplifier Offset and FiniteGain Effects in SwitchedCapacitor Circuits,” (invited paper) Periodica Polytechnica, 1986.
 Temes, G.C., “Simple Formula for Estimation of Minimum Clock Feedthrough Error Voltage,” Electronics Letters, 22: 10691070, September 1986.
 Larson, L.E., Temes, G.C., and Law, S., “Comparison of Amplifier Gain Enhancement Techniques for GaAs MESFET Analogue Integrated Circuits,” Electronics Letters, 22: 11381139, October 1986.
 Larson, L.E. and Temes, G.C., “SwitchedCapacitor Gain Stage with Reduced Sensitivity to Finite Amplifier Gain and Offset Voltage,” Electronics Letters, 22: 12811283, November 1986.
 Martin, K., Ozcolak, L., Lee, Y.S., and Temes, G.C., “A Differential SwitchedCapacitor Amplifier,” IEEE J. of SolidState Circuits, SC22: 104106, February 1987.
 Robert, J., Temes, G.C., Valencic, V., Dessoulavy, R., and Deval, P., “A 16Bit LowVoltage CMOS A/D Converter,” IEEE J. of SolidState Circuits, SC22: 157163, April 1987.
 Temes, G.C. and Ki, W.H., “Fast CMOS Current Amplifier and Buffer Stage,” Electronics Letters, 23: 696697, June 1987.
 Larson, L.E., Martin, K.W., and Temes, G.C., “GaAs SwitchedCapacitor Circuits for HighSpeed Signal Processing,” J. of SolidState Circuits, SC22: 971981, December 1987.
 Kunsagi, L. and Temes, G.C., “BufferBased SwitchedCapacitor Gain Stages,” Electronics Letters, 24: 254255, March 1988.
 Larson, L.E., Cataltepe, T., and Temes, G.C., “Multibit Oversampled ΣΔ A/D Converter with Digital Error Correction,” Electronics Letters, 24: 10511052, August 1988.
 Wang, F.J. and Temes, G.C., “A Fast OffsetFree SampleandHold Circuit,” J. of SolidState Circuits, SC23: 12701272 (Corr.), October 1988.
 Ki, W.H. and Temes, G.C., “SwitchedCapacitor Modulator Circuits,” Electronics Letters, 25: 379381, March 1989.
 Wang, F.J., Temes, G.C., and Law, S., “A QuasiPassive CMOS Pipelined D/A Converter,” J. of SolidState Circuits, SC24: 17521755 (Corr.), December 1989.
 Watanabe, K., Temes, G.C., and Tagami, T., “A New Algorithm for Cyclic and Pipeline Data Conversion,” IEEE Trans. on Circuits and Systems, 37: 249252, February 1990.
 Hadidi, K., Tso, V., and Temes, G.C., “An 8b 1.3 MHz SuccessiveApproximation A/D Converter,” J. of SolidState Circuits, SC25: 880885 (Corr.), June 1990.
 Ki, W.H. and Temes, G.C., “LowPhaseError OffsetCompensated SwitchedCapacitor Integrator,” Electronics Letters, 26: 957959, June 1990.
 Zhang, Z. and Temes, G.C., “Multibit Oversampled ΣΔ A/D Convertor with Nonuniform Quantization,” Electronics Letters, 27:528529, March 1991.
 Comino, V., Steyaert, M.S.J., and Temes, G.C., “A FirstOrder CurrentSteering SigmaDelta Modulator,” IEEE J. of SolidState Circuits, SC26:176183, March 1991.
 Hairapetian, A., Temes, G.C., and Zhang, Z., “Multibit SigmaDelta Modulator with Reduced Sensitivity to DAC Nonlinearity,” Electronics Letters, 27:990991, May 1991.
 Czarnul, Z., Temes, G.C., and Yesilyurt, A.G., “PseudoNPath SwitchedCapacitor Filters with OutofBand Noise Peaks,” Electronics Letters, 27:11371139, June 1991.
 Zhang, Z.X., Temes, G.C., and Czarnul, Z., “Bandpass ΔΣ A/D Convertor Using TwoPath Multibit Structure,” Electronics Letters, 27:20082009, October 1991.
 Czarnul, Z., Yesilyurt, A.G., and Temes, G.C., “Multiplexed Noise Shaping Structures for DeltaSigma Modulators,” Electronics Letters, 27:23422343, December 1991.
 Xu, X. and Temes, G.C., “DualTruncation ΔΣ DigitaltoAnalogue Convertors,” Electronics Letters, 28:9294, January 1992.
 Abdennadher, S., Kiaei, S., Temes, C.G., and Schreier, R., “Adaptive SelfCalibrating ΔΣ Modulators,” Electronics Letters, 28:12881289, July 1992.
 Yang, Y., Schreier, R., Temes, G.C., and Kiaei, S., “OnLine Adaptive Digital Correction of DualQuantization ΔΣ Modulators,” Electronics Letters, 28:15111513, July 1992.
 Hadidi, K. and Temes, G.C., “Error Analysis in Pipeline A/D Converters and Its Applications,” IEEE Trans. on Circuits and Systems, II, 39:506515, August 1992.
 SarhangNejad, M. and Temes, G.C., “A HighResolution MultiBit ΣΔ ADC with Digital Correction and Relaxed Amplifier Requirements,” IEEE J. of SolidState Circuits, SC28:648660, June 1993.
 Cao, Y.M. and Temes, G.C., “HighAccuracy Circuits for OnChip Capacitance Ratio Testing or Sensor Readout,” IEEE Trans. on Circuits and Systems, II, 41:637639, September 1994.
 Kenney, J.G, Rangan, G., Ramamurthy, K., and Temes, G.C., “An Enhanced Slew Rate Source Follower,” IEEE J. of SolidState Circuits, SC30:144146, February 1995.
 Ki, W.H. and Temes, G.C., “Optimal Capacitance Assignment of SwitchedCapacitor Biquads,” IEEE Trans. on Circuits and Systems, I, 42:334342, June 1995.
 Temes, G.C., Huang, Y., and Ferguson, Jr., P.F., “A HighFrequency TrackandHold Stage with Offset and Gain Compensation,” IEEE Trans. on Circuits and Systems, II, 42:559561, August 1995.
 Enz, Ch. and Temes, G.C., “Circuit Techniques for Reducing the Effects of OpAmp Imperfections: Autozeroing, Correlated Double Sampling and Chopper Stabilization,” invited paper, Proc. IEEE, 84:15841614, November 1996.
 Yoshizawa, H., Huang, Y., and Temes, G.C., “Improved SC Amplifiers with Low Sensitivity to OpAmp Imperfections,” Electronics Letters, 33:348349, February 1997.
 Huang, Y., Ferguson, Jr., P.F., and Temes, G.C., “Reduced Nonlinear Distortion in Circuits with Correlated Double Sampling,” IEEE Trans. on Circuits and Systems, II, 44:593597, July 1997.
 Wang, B., Kajita, T., Sun, T., and Temes, G.C., “HighAccuracy Circuits for OnChip Capacitive Ratio Testing and Sensor Readout,” IEEE Trans. on Instrumentation and Measurement, 47:1620, February 1998.
 Steensgaard, J., Moon, U., and Temes, G.C., “MismatchShaping Switching for TwoCapacitor DAC,” Electronics Letters, 34:16331634, August 1998.
 Yoshizawa, H., Huang, Y., Ferguson, P., and Temes, G.C., “MOSFETOnly SwitchedCapacitor Circuits in Digital CMOS Technology,” IEEE J. of SolidState Circuits, 34(6):734747, June 1999.
 Basu, S. and Temes, G., “Simplified Clock Voltage Doubler,” Electron. Lett., 35(22):19011902, October 28, 1999.
 Moon, U.K., Silva, J., Steensgaard, J. and Temes, G.C., “SwitchedCapacitor DAC with Analogue Mismatch Correction,” Electron. Lett., 35:19031904, October 28, 1999.
 Moon, U., Steensgaard, J., and Temes, G., “Digital Techniques for Improving the Accuracy of Data Converters,” IEEE Comm. Magazine, pp. 136143, October 1999.
 Cauwenberghs, G. and Temes, G.C., “Adaptive Digital Correction of Analog Errors in MASH ADCs  Part I: OffLine and Blind OnLine Calibration,” IEEE Trans. on Circuits and Systems, II, 47(7): 621628, July 2000.
 Kiss, P., Silva, J., Weisbauer, A., Sun, T., Moon, U., Stonick, J., and Temes, G., “Adaptive Digital Correction of Analog Errors in MASH ADCsPart II: Correction Using TestSignal Injection,” IEEE Trans. Circuits and Systems II, 47(7): 629638, July 2000.
 Kiss, P., Moon, U., Steensgaard, J., Stonick, J., and Temes, G., “HighSpeed ΔΣ ADC with Error Correction,” Electron. Lett., 37(2): 7666, January 18, 2001.
 Kajita, T., Temes, G., and Moon, U., “Correlated Double Sampling Integrator Insensitive to Parasitic Capacitance,” Electron. Lett., 37(3): 151153, February 1, 2001.
 Keskin, M., Moon, U., and Temes, G., “SwitchedCapacitor Resonator Structure with Improved Performance,” Electron. Lett., 37(4): 212213, February 15, 2001.
 Wang, X., Kiss, P., Moon, U., Steensgaard, J., and Temes, G., “Digital Estimation and Correction of DAC Errors in Multibit ΔΣ ADCs,” Electron. Lett., 37(7): 414415, March 29, 2001.
 Silva, J., Moon, U., Steensgaard, J., and Temes, G., “Wideband LowDistortion ΔΣ ADC Topology,” Electron. Lett., 37(12): 737738, June 7, 2001.
 Keskin, M., Keskin, N., and Temes, G.C., “An Efficient and Accurate DC Analysis Technique for SC Circuits,” Analog Int. Circuits & Sig. Proc., 30: 239242, March 2002.
 Keskin, M., Moon, U., and Temes, G.C., “DirectChargeTransfer PseudoNPath SC Circuit Insensitive to Element Mismatch and Opamp Nonidealities,” Analog. Int. Circuits & Sig. Proc., 30: 243247, March 2002.
 Kajita, T., Moon, U., and Temes, G., “A NoiseShaping Accelerometer Interface Circuit for TwoChip Implementation,” VLSI Design, pp. 355361, June 2002.
 Keskin, M., Moon, U., and Temes, G.C., “A 1V 10MHz ClockRate 13Bit CMOS DeltaSigma Modulator Using UnityGainReset Opamps,” IEEE J. SolidState Circuits, 37(7): 817824, July 2002.
 Kajita, T., Moon, U., and Temes, G.C., “A TwoChip Interface for a MEMS Accelerometer,” IEEE Trans. Instr. & Meas., 51(4): 853858, August 2002.
 Markus, J. and Temes, G.C., “An Efficient DeltaSigma ADC Architecture for Low Oversampling Ratios,” IEEE Trans. Circuits and Sys.I, 51(1): 6371, Jan. 2004.
 Markus, J., Silva, J. and Temes, G.C., “Theory and Applications of Incremental DeltaSigma Converters,” IEEE Trans. Circuits and Sys.I, 51(4): 678690, April 2004.
 Temes, G. and Silva, J., “A Simple and Efficient Noise Estimation Algorithm,” Electron. Lett., 40(11):640642, May 27, 2004.
 Rao, A., McIntyre, W., Moon, U. and Temes, G.C., “NoiseShaping Techniques Applied to SwitchedCapacitor Voltage Regulators,” IEEE J. SolidState Circuits, 40(2):422429, Febr. 2005.
 Sharma, V., Narayan, A., Rengachari, T., Temes, G., Chaplen, F., Temes, G. and Moon, U., “A LowCost Portable Generic Cytosensor for Environmental Monitoring Applications,” Biosensors and Bioelectronics, 20, pp. 22182227, May 2005.
 Ahn, G., Chang, D., Brown, M., Ozaki,, N., Youra, H., Yamamura, K., Hamashita, K., Temes, G. and Moon, U., “A 0.6 V 82 dB DeltaSigma Audio ADC Using SwitchedRC Integrators,” IEEE J. SolidState Circuits, 40(12), pp. 23982407, Dec. 2005.
 Schreier, R., Steensgaard, J. and Temes, G., “DesignOriented Estimation of Thermal Noise in SwitchedCapacitor Circuits,” IEEE Trans. on Circuits and Sys.I, 52(11), pp. 23582378, Nov. 2005.
 Wang, R. and Temes, G., “SplitSet DataWeighted Averaging,” IEE El. Letters, 42(4), pp. 248249, Febr. 16, 2006.
 Nishida, Y. and Temes, G.C., “Correlated Double Sampling Technique for ContinuousTime Filters,” IEE El. Letters, 42(13), pp. 727728, June 22, 2006.
 Lee, K. and Temes, G.C., “Enhanced SplitArchitecture DeltaSigma ADC,” IEE El. Letters, 42(13), pp. 737739, June 22, 2006.
 Maghari, N., Kwon, S., Temes, G.C. and Moon, U., “Sturdy MASH DeltaSigma Modulator,” IEE El. Letters, 42(22), pp. 12691270, Oct. 26, 2006.
 Lee, K., Bonu, M. and Temes, G.C., “NoiseCoupled DeltaSigma ADCs,” IEE El. Letters, 42(24), pp. 13811382, Nov. 23, 2006.
 Quiquempoix, V., Deval, Ph., Barreto, A., Bellini, G., Collings, J., Markus, J., Silva, J. and Temes, G., “A LowPower 22Bit Incremental ADC,” IEEE J. of SolidState Circuits, 41(7), pp. 15621571, July 2006.
 Han, J., von Jouanne, A. and Temes, G., “A New Approach to Reducing Output Ripple in SwitchedCapacitor Based StepDown DCDC Converters,” IEEE Trans. on Power Electronics, 21(6), pp. 15481555, Nov. 2006.
 Yoshizawa, H. and Temes, G., “SwitchedCapacitor TrackandHold Amplifier with Low Sensitivity to OpAmp Imperfections,” Analog Integrated Circuits and Signal Processing , 48(3), pp. 267270, Sept. 2006.
 Wang, Y. and Temes, G.C., “Dynamic Biasing Scheme for HighSpeed LowVoltage SwitchedCapacitor Stages,” IEE El. Letters, 43(4), pp. 214216, Febr. 15, 2007.
 Yoshizawa, H. and Temes, G.C., “Switchedcapacitor TrackandHold Amplifiers with Low Sensitivity to Opamp Imperfections,” IEEE Trans. on Circuits and SystemsI, 54(1), pp. 193199, Jan. 2007.
 Kurahashi, P., Hanumolu, P., Temes, G. and Moon, U., "A 0.6V Highly Linear SwitchedRMOSFETC Filter," IEEE J. of SolidState Circuits, 42(8), pp. 16991709, Aug. 2007.
 Wang. R., Moon, U. and Temes, G.C., “A 100dB GainCorrected DeltaSigma Audio DAC with Headphone Driver,” Analog Integrated Circuits and Signal Processing, 51(1), pp. 2732, April 2007.
 Lee, K., Chae, J. and Temes, G.C., “Efficient Floating DoubleSampling Integrator for DS ADCs,” Electronics Letters, 43(25), pp. 14131414, Dec.6, 2007.
 Kim, M., Ahn, G., Hanumolu, P., Lee, S., Kim, S., You, S., Kim, J., Temes, G.C. and Moon, U. “A 0.9V 92dB DoubleSampled SwitchedRC DeltaSigma Audio ADC,” IEEE J. of SolidState Circuits, 43(5), pp. 11951206, May 2008.
 Steensgaard, J., Zhang, Z., Yu, W., Sarhegyi, A. Lucchese, L., Kim, D., and Temes, G.C., “NoisePower Optimization of Incremental Data Converters,” IEEE Trans. on Circuits and Systems I, vol. 55, no. 5, pp. 12891296, June 2008.
 Lee, K. and Temes, G.C., “Enhanced SplitArchitecture DeltaSigma ADC,” Analog Integrated Circuits and Signal Processing, 56(3), pp. 251257, Sept. 2008.
 Lee, K., Chae, J., Aniya, M., Hamashita, K. Takasuka, K., Takeuchi, S., Temes, G.C “A NoiseCoupled DeltaSigma ADC with 4.2 MHz Bandwidth, 98 dB THD and 79 dB SNDR,” IEEE J. of SolidState Circuits, 43(12), pp. 26012612, Dec. 2008.
 Maghari, N., Temes, G.C and Moon, U, “SingleLoop DeltaSigma Modulator with Extended Dynamic Range,” El. Letters, 44(25), pp. 14521453, Dec.4, 2008.
 Wang, Y. and Temes, G.C., “NoiseCoupled ContinuousTime DeltaSigma ADCs,” El. Letters, 45(6), pp. 349352, March 12, 2009.
 Lee. K., Miller, M. and Temes, G.C., “An 8.1 mW, 82 dB DeltaSigma ADC with 1.9 MHz BW and 98 dB THD,” IEEE J. of SolidState Circuits, 44(8), pp. 22022211, Aug. 2009.
 Zhang, Z., Steensgaard, J., Temes, G.C. and Wu, J., “A 14Bit DualPath 20 MASH ADC with Dual Digital Error Correction,” Analog Integrated Circuits and Signal Processing, 59(2), pp. 143150, May 2009.
 Lee, K., Meng, Q., Sugimoto, T., Hamashita, K., Takasuka, K., Takeuchi, S., Moon, U. and Temes, G., “A 0.8V, 2.6 mW, 88dB DualChannel Audio DeltaSigma DAC with Headphone Driver," IEEE J. of SolidState Circuits, 44(3), pp. 916927, March 2009.
 Lee, K. and Temes, G.C., “Improved Architecture for LowDistortion DeltaSigma ADCs,” El. Letters, 45(14), pp. 730731, July 2, 2009.
 Maghari, N.,Temes, G.C. and Moon, U., “NoiseShaped Integrating Quantizers in DeltaSigma Modulators,” El. Letters, 45(12), June 4, 2009.
 Shen, W. and Temes, G.C.,”DoubleSampled DeltaSigma Modulator with Relaxed Feedback Timing,” El. Letters, 45(17), pp. 875877, Aug. 18, 2009.
 Yu, W. and Temes, G.C., “PowerUp Calibration Techniques for DoubleSampled DeltaSigma Modulators,” El. Letters, 45(19), Sept. 18, 2009.
 Yu, W., Lin, J. and Temes, G.C., “TwoStep SplitJunction SAR ADC,” El. Letters, 46(3), pp. 211212, Febr. 4, 2010.
 Wang, T. and Temes, G.C., “SwitchedR Tuning Technique for GmC Filters,” El. Letters, 46(4), pp. 275276, Febr. 18, 2010.
 Wang, Y., Hamashita, K. and Temes, G.C., “Hybrid DeltaSigma ADC,” Analog Integrated Circuits and Signal Processing, 63(2), pp. 293296, May 2010.
 Temes, G.C., “MicroPower Data Converters: a Tutorial,” IEEE Trans. on Circuits and Systems – II, (57)6, pp. 405410, June 2010.
 Nishida, Y. Hamashita, K. and Temes, G.C., “An Enhanced DualPath DeltaSigma A/D Converter,” IEICE Trans. on Electronics, E93C(6), pp. 884892, June 2010.
 Wang, T. and Temes, G.C., “LowPower ParasiticInsensitive SwitchedCapacitor Integrator for DeltaSigma ADCs,” El. Letters, 46(16), pp. 11141116, Aug. 5, 2010.
 Chae, J. and Temes, G.C., “ComparatorBased Buffer with Resistive Error Correction,” El. Letters, 46(17), pp. 11881190, Aug. 19, 2010.
 Lin, J., Yu, W. and Temes, G.C.,”MultiStep CapacitorSplitting SAR ADC,” El. Letters, 46(21), pp. 14261428, Oct. 14, 2010.
 Jung, Y., Lee, S., Chae, J. and Temes, G.C., “LowPower and LowOffset Comparator Using Latch Load,” El. Letters, 47(3), pp. 167168, 2011.
 Yoshizawa, H., Yabe, T. and G.C. Temes, “HighPrecision SwitchedCapacitor Integrator Using LowGain Opamp,” El. Letters, 47(5), 2011.
 Wang, Y., Hanumolu, K. and Temes, G.C., “Design Techniques for Wideband DiscreteTime DeltaSigma ADCs with Extra Loop Delay,” IEEE Trans. on Circuits and Systems – I, (58)7, pp. 15181530, July 2011.
 Tong, T., Hanumolu, P.K. and Temes, G.C., “A SemiSynchronous SAR ADC,” Analog Integrated Circuits and Signal Processing, 71(3), pp. 407410, June 2012.
 Jung, Y., Lee,S., Chen, C.H. and Temes, G.C., “Double Noise Coupling ΔΣ AnaloguetoDigital Converter,” Electronics Letters, vol. 48, no. 10, pp. 557558, May 2012.
 Wei Li, Tao Wang, J. Cao and Gabor C. Temes, “Teraohm OnChip Resistance Realization Using Switched Capacitor Topologies,” Electronic Letters, vol. 48, no. 11, pp. 623–624, May 2012.
 Yu, W. and Temes, G.C., “A Digital DAC Calibration Technique for ΔΣ and Incremental Modulators,” Electronics Letters, vol.48, no.13, pp. 754755, June 2012.
 Meng, X., Wang, T. and Temes, G.C., “Charge Compensation Technique for SwitchedCapacitor Circuits,” Electronic Letters, vol. 48, no. 16, pp. 988990, August 2012.
 Zanbaghi, R., Saxena, S., Temes, G.C. and Fiez, T.S., “A 75 dB SNDR, 10 MHz Conversion Bandwidth StageShared 22 Mash ΔΣ Modulator Dissipating 9 mW,” IEEE Trans. on Circuits and Systems – I, vol. 59, no. 8, pp. 16141625, Aug. 2012.
 Tong, T., Yu, W., Hanumolu, P.K. and Temes, G.C., “Calibration Techniques for SAR ADCs,” Analog Integrated Circuits and Signal Processing, 73(1), pp. 301309, October 2012
 Zhang, Y., ChiaHung Chen and Gabor C. Temes, “Accuracyenhanced switchedcapacitor stages using lowgain opamps,” Electronic Letters, vol. 49, no. 1, pp. 2223, Jan 2013.
 Chen, CH., Y. Jung, J. L. Ceballos, and G. C. Temes. “Multistep extendedcounting analoguetodigital converters,” Electronics Letters, vol. 49, no. 1 (2013): 3031.
 Chen, C. H., Y. Zhang, J. L. Ceballos, and G. C. Temes. “Noiseshaping SAR ADC using three capacitors,” Electronics Letters, vol. 49, no. 3 (2013): 182184.
 Chen, CH., Y. Zhang, Y. Jung, T. He, J. L. Ceballos, and G. C. Temes, “Twostep incremental analoguetodigital converter,” Electronics Letters, vol. 49, no. 4 (2013): 250251.
 Zhang, Y., Chen, C. H. and Temes, G. C., “An efficient technique for excess loop delay compensation in continuoustime ΔΣ modulators,” Electronics Letters, vol. 49, no. 24 (2013) 15221523.
 Meng, X and Temes, G.C., “Doublesampled wideband deltasigma ADCs with shifted loop delays,” Electronics Letters, vol. 50, no. 11 (2014), 794795.
 Meng, X, Zhang, Y., He, T. and Temes, G.C., “Lowdistortion wideband deltasigma ADCs with shifted loop delays,” IEEE Trans. on Circuits and Systems – I, (62)2, 376384. Febr. 2015.
 Chen, CH, Zhang , Y., He, T., Chiang, P.Y. and Temes, G.C., “A micropower twostep incremental analogtodigital converter,” IEEE J. of SolidState Circuits, vol. 50, no. 8, Aug. 2015, pp. 17961808.
 Zhang, Y., Chen, C. H. He, T. and Temes, G. C., “A continuoustime ΔΣ modulator for biomedical ultrasound beamformer using digital ELD compensation and FIR feedback,” IEEE Trans. on Circuits and Systems – I, vol. 62, no. 7, July 2015, pp. 16891698.
 Chen, CH, Zhang , Y., He, T. and Temes, G.C., “A twostep multistage incremental analogtodigital converter,” El. Letters, vol. 51, no. 24, pp. 19751977, Nov. 2015.
 Chen, CH, Zhang , Y., He, T. and Temes, G.C., “Incremental analogtodigital converters for highresolution energyefficient sensor interfaces,” IEEE J. of Emerging and Selected Topics in Circuits and Systems, vol. 5, no. 4, pp. 612623, Dec. 2015.
 He, T., Chen, CH, Zhang, Y. and Temes, G.C., “Digital ELD compensation techniques with embedded truncator for continuoustime deltasigma modulators,” El. Letters, vol. 52, no. 1, pp. 2021, Jan. 2016.
 Zhang, Y., He, T., Chen and Temes, G.C., “Multistep incremental ADC with extended binary counting,” El. Letters, vol. 52, 2016, Volume: 52, no.9, pp 697–699.
 Payandehnia, P., Maghami, H., Kareppagoudr, M. and Temes, G.C., “A passive switchedcapacitor filter with complex poles for highspeed applications,” Electronics Letters, 2016, vol. 52, no.19, pp. 1592–1594.
 Zhang, Y.,CH Chen, He, T. and G.C. Temes, “A 16bit multistep Incremental ADC with singleopamp multislope extended counting,” IEEE J. of SolidState Circuits, vol. 52, no. 4, April 2017, pp. 1066  1076.
 Jung, Y. and Temes, G.C. “A wideband highaccuracy incremental ADC,” Analog Integrated Circuits and Signal Processing, Febr. 2017, vol. 90, no. 2, pp. 291  300.
 Payandehnia, P. and Temes, G.C., “Fully Passive 3rdOrder Noise Shaping SAR ADC,” Electronics Letters, Apr. 13,2017, vol. 53, no. 8. pp. 528 – 530.
 Jung, Y. and Temes, G.C., “Powerefficient noisecoupled ΔΣ ADC with simple delay cells,” El. Letters, May 25, 2017, vol. 53, no. 11, pp. 712713.
 Jung, Y. and Temes, G.C. “Improved double noise coupling ΔΣ ADC, Analog Integrated Circuits and Signal Processing, vol. 91, no. 3, June 2017.
 Sadollahi, M., Hamashita, K. Sobue, K. and Temes, G.C., “An 11bit 250 nW 10 kS/s SAR ADC with doubled input range for biomedical applications,” IEEE Transactions on Circuits and SystemsI, to appear.
 Wang, Y., He, T., Silva, P., Zhang, Y. and Temes, G.C., “Wideband highaccuracy ΔΣ ADC using segmented DAC with DWA and mismatch shaping,” El. Letters, 2017,vol. 53, no.11, pp. 713714.
Conference Proceedings
 Temes, G.C., “Interaction Between the EnergyLosses of Protons in Free Electron Gas,” KFKI Kozlemenyek, Proc. of the Central Research Inst. of Physics, Budapest, 1957, 5:7783.
 Temes, G.C., Boire, P., and Banfill, H., “A New Brightness Meter,” Proc. of the Instrument Soc. of America, June 1960, pp. 61 to 68.
 Temes, G.C., “A Method for the Estimation and Precorrection of Losses in Terminated LC Networks,” Proc. of the Natl. Electronics Conf., sponsored by AIEE, October 911, 1961, Chicago, 17:98110.
 Temes, G.C., “Filter Synthesis Using a Digital Computer,” 1962 Inst. of Radio Engineers Int. Convention Record, sponsored by IRE Professional Group on Circuit Theory, March 29, 1962, New York, 9:211227.
 Temes, G.C., “An Extension of Darlington's Semiuniform Predistortion Procedure,” Proc. of the 1st Annual Allerton Conf. on Circuit & System Theory, sponsored by Department of Electrical Engineering and Coordinated Science Lab., November 1517, 1963, University of Illinois, 1:246258.
 Smith, B.R. and Temes, G.C., “An Iterative Approximation Procedure for Automatic Filter Synthesis, IEEE Int. Convention Record, 1964, sponsored by IEEE, Inc., March 2326, 1964, New York, 12:270281, pt. 1.
 Temes, G.C. and Bingham, J.A.C., “Iterative Chebyshev Approximation for Network Synthesis,” Proc. of the Allerton Conf. on Circuit and System Theory, IEEE Circuit Theory group and the University of Illinois, October 2022, 1965, 3:773785.
 Temes, G.C., “Iterative Optimization Techniques,” Proc. of the Inst. of Modern SolidState Circuit Design, sponsored by University of Santa Clara and NASA, September 1516, 1966, 1:96114.
 Temes, G.C. and Orchard, H.J., “Maximally Flat Approximation Techniques,” Proc. of the Allerton Conf. on Circuit and System Theory, University of Illinois, November 1966, 4:465.
 Temes, G.C. and Gyi, M., “Design of Filters with Arbitrary Passband and Chebyshev Stopband Attenuation,” 1967 IEEE Int. Convention Record, March 1967, 15(5):212.
 Temes, G.C., “Bandlimited System with Optimum Time Response,” 7th Annual Proc. of the Allerton Conf. on Circuit and System Theory, sponsored by Circuit Theory and Automatic Control Groups of the IEE, October 810, 1969, University of Illinois, pp. 805818.
 Temes, G.C., “Computer Synthesis and Optimization of Filters,” Abstract, 3rd Asilomar Conf. Record on Circuits and Systems, sponsored by IEEE Groups on Circuit Theory and Automatic Control, December 1012, 1969, p. 293.
 Temes, G.C., “Automated Circuit Design,” Abstract, Proc. of 1970 Chiao Tung Colloquium on Circuits & Systems, August 2526, 1970, Taiwan, p. 291.
 Marshall F.C. and Temes, G.C., “ComputerAided Chebyshev Optimization in the Time Domain,” Proc. of the Kyoto Int. Conf. on Circuit and System Theory, sponsored by Inst. of Electronics and Communication Engineers of Japan, September 911, 1970, pp. 1314.
 Gadenz, R.N. and Temes, G.C., “Statistical Transient Analysis of Nonlinear Circuits,” Proc. Mexico Int. IEEE Conf. on systems, Networks and Computers, January 1921, 1971, Oaxtepec, Mexico.
 Barcilon, V. and Temes, G.C., “On Bandwidth, Risetime and Overshoot,” Proc. of the London 1971 IEEE Int. Symposium on Electrical Network Theory, The Circuit Theory Group and the UK and RI Section of IEEE, September 610, 1971, City University, London, England, pp. 3940.
 Temes, G.C., Kurtz, J., and Orchard, H.J., “Least Squares Passband Filters,” Proc. of the London 1971 IEEE Int. Symposium on Electrical Network Theory, September 610, 1971, City University, London, England, pp. 111112.
 Temes, G.C., Ebers, R.M., and Gadenz, R.N., “Some Novel Applications of the Adjoint Network Concept in FrequencyDomain Circuit Analysis and Optimization, Proc. of the London 1971 IEEE Int. Symposium on Electrical Network Theory, September 610, 1971, City University, London, England, pp. 111112.
 Gadenz, R.N. and Temes, G.C., “A Computational Algorithm for the Design of Elliptic Filters,” Proc. of the 1972 Int. Filter Symposium, sponsored by NSF, University of Maryland, and UCLA, April 518, 1972, Santa Monica, CA, pp. 2829.
 Temes, G.C. and Orchard, H.J., “Sensitivity and Reflection Coefficients, Proc. of the 1972 Int. Filter Symposium, sponsored by NSF, University of Maryland, and UCLA, April 518, 1972, Santa Monica, CA, pp. 9293.
 Gadenz, R.N. and Temes, G.C., “Efficient Hybrid and StateSpace Analysis of the Adjoint Network,” Proc. of the 1972 Int. Symposium on Circuit Theory, sponsored by IEEE, April 1822, 1972, Los Angeles, pp. 184188.
 Barcilon, V. and Temes, G.C., “Recent Results in the Optimization of Bandlimited Systems,” Proc. of the 1973 Int. Symposium on Circuit Theory, Sponsored by IEEE, April 911, 1973, Toronto, Canada, pp. 194197.
 Gadenz, R.N., RezaiFakhr, G., and Temes, G.C., “A Method for the Computation of Large Tolerance Effects,” Proc. of the 1973 Int. Symposium on Circuit Theory, sponsored by IEEE, April 911, 1973, Toronto, Canada, pp. 220222.
 Orchard, H.J. and Temes, G.C., “Vestigial Sideband Filters,” 1974 European Conf. on Circuit Theory and Design, July 2326, 1974, London, England, pp. 2631.
 RezaiFakhr, M.G. and Temes, G.C., “Statistical LargeTolerance Analysis of Linear and Nonlinear Circuits in the Time Domain,” 1974 European Conf. on Circuit Theory and Design, July 2326, 1974, London, England, pp. 295300.
 Temes, G.C. and Marshall, F.C., “Window Functions for the Fast Fourier Transform,” Proc. of the II Interamerican Conf. on Syst. and Inf., November 1974, Mexico City.
 Babic, H. and Temes, G.C., “Optimum LowOrder Discrete Windows for the Estimation of Power Spectra,” Proc. of the 3rd Int. Symposium on Network Theory, September 15, 1975, Split, Yugoslavia, pp. 745757.
 Temes, G.C., “A WorstCase Error Analysis for the FFT,” Proc. of the 1976 IEEE Int. Symposium on Circuits & Systems, April 2729, 1976, Munich, W. Germany, pp. 98101.
 Temes, G.C., “Efficient Methods of Fault Analysis,” Proc. of the 20th Midwest Symposium on Circuits and Systems, August 1977, Lubbock, TX, pp. 191194.
 Temes, G.C., “Efficient Methods of Fault Analysis,” Proc. of the 4th Symposium on Reliability in Electronics, October 1977, Budapest, Hungary, pp. 241248.
 Temes, G.C. and Cheung, D.T., “Integrated Input Circuits for Photo Detectors,” Proc. of the 11th Asilomar Conf. on Circuits, Systems & Computers, November 1977, Pacific Grove, CA, pp. 451455.
 Cho, K.M. and Temes, G.C., “RealFactor FFT Algorithms,” Proc. of the 1978 Int. Conf. on Acoustics, Speech & Signal Processing, April 1978, Tulsa, OK, pp. 634637.
 Temes, G.C., “DigitalFilter Design Techniques for the Synthesis of SwitchedCapacitor Active Circuits,” Proc. of the 1978 Int. Conf. on Digital Signal Processing, August 1978, Florence, Italy, pp. 569577.
 Orchard, H.J. and Temes, G.C., “Spectral Analysis of SwitchedCapacitor Filters Designed Using the Bilinear zTransform,” Proc. of the 12th Annual Asilomar Conf. on Circuits, Systems, and Computers, November 1978, pp. 674678.
 Young, I.A., Simonyi, A., and Temes, G.C., “SwitchedCapacitor Filter Sections Implementing the Bilinear zTransform,” Proc. of the 12th Annual Asilomar Conf. on Circuits, Systems and Computers, November 1978, pp. 689692.
 Szentirmai, G. and Temes, G.C., “SwitchedCapacitor Building Blocks,” Proc. of the 13th Annual Asilomar Conf. on Circuits, Systems and Computers, November 1979, pp. 542545.
 Temes, G.C. and Gregorian, R., “Compensation for Parasitic Capacitances in SwitchedCapacitor Filters,” Proc. of the 13th Annual Asilomar Conf. on Circuits, Systems and Computers, November 1979, pp. 546548.
 Gregorian, R. and Temes, G.C., “SelfEqualizing SampleandHold Circuits, Proc. of the 13th Annual Asilomar Conf. on Circuits, Systems and Computers, November 1979, pp. 549551.
 Nossek, J. and Temes, G.C., “SwitchedCapacitor Filter Design Using Bilinear Element Modeling,” Proc. of the 1980 Int. Symposium on Circuits and Systems, April 1980, Houston, TX, pp. 330333.
 Fan, S.C., Gregorian, R., Temes, G.C., and Zomorrodi, M., “SwitchedCapacitor Filters Using UnitGain Buffers,” Proc. of the 1980 Int. Symposium on Circuits and Systems, April 1980, Houston, TX, pp. 334337.
 Lee, M.S., Temes, G.C., Chang, C., and Ghaderi, M.B., “Bilinear SwitchedCapacitor Ladder Filters,” Proc. of the 14th Asilomar Conf. on Circuits, Systems and Computers, November 1980, pp. 435439.
 Muller, G. and Temes, G.C., “A Simple Method for the Computation of the Frequency Response of a Class of SwitchedCapacitor Filters,” Proc. of the 14th Asilomar Conf. on Circuits, Systems and Computers, November 1980, pp. 440442.
 Ghaderi, M.B., Temes, G.C., Lee, M.S., and Chang, C., “Bilinear SwitchedCapacitor Ladder Filters  New Results,” Proc. of the 1981 IEEE Int. Symposium on Circuits and Systems, April 1981, Chicago, IL, pp. 170174 (invited paper).
 Ghaderi, M.B., Temes, G.C., and Nossek, J.A., “SwitchedCapacitor PseudoNPath Filters,” Proc. of the 1981 IEEE Int. Symposium on Circuits and Systems, April 1981, Chicago, IL, pp. 519522 (invited paper).
 Temes, G.C., “SwitchedCapacitor Filters,” Proc. 24th Midwest Symposium on Circuits and Systems, June 1981, Albuquerque, NM, pp. 577578 (invited).
 Temes, G.C., “SwitchedCapacitor Filters: History and the State of the Art,” Proc. 1981 European Conf. on Circuit Theory and Design, August 1981, The Hague, Netherlands, pp. 176185 (invited).
 Temes, G.C. and Mueller, G., “The Poor Man’s Algorithm for the ComputerAided Analysis of Switched Capacitor Filters,” 15th Asilomar Conf. on Circuits, Systems, and Computers, November 911, 1981, Pacific Grove, CA.
 Law, S., Temes, G.C., Ngo, T.M., and Ibrahim, A., “A HighSpeed CCD Interpolator Filter,” IEEE Internat. Conf. on Circuits and Computers, September 1982, New York, pp. 482485.
 Hsu, T.H. and Temes, G.C., “LowSensitivity Digital Filter Design from a SwitchedCapacitor Filter Prototype,” 1983 IEEE Internat. Symp. on Circuits and Systems, May 1983, Newport Beach, CA, pp. 282285.
 Watanabe, K. and Temes, G.C., “A SwitchedCapacitor Digital Multiplier,” 1983 IEEE Internat. Symp. on Circuits and Systems, Newport Beach, CA, May 1983, pp. 12701273.
 Watanabe, K. and Temes, G.C., “A SwitchedCapacitorDigitalCapacitanceBridge,” Proc. of the 1984 IEEE Internat. Symp. on Circuits and Systems, May 710, 1984, Montreal, Canada, pp. 173176.
 Orchard, H.J., Temes, G.C., and Cataltepe, T., “General Sensitivity Theorems for Terminated Lossless TwoPorts,” Proc. of the 1984 IEEE Internat. Symp. on Circuits and Systems, May 710, 1984, Montreal, Canada, pp. 177180.
 Haug, K., Temes, G.C., and Martin, K.W., “Improved Offset Compensation Schemes for SwitchedCapacitor Circuits,” Proc. of the 1984 IEEE Internat. Symp. on Circuits and Systems, May 710, 1984, Montreal, Canada, pp. 10541057.
 Babanezhad, J.N. and Temes, G.C., “Linear MOS Simulated Resistors,” Proc. of the 1985 IEEE International Symp. on Circuits and Systems, June 57, 1985, Kyoto, Japan, pp. 14191422.
 Shyu, J.B., Temes, G.C., and Krummenacher, I., “Random Error Effects in Matched MOS Capacitors and Current Sources,” Proc. of the 1985 IEEE International Symp. on Circuits and Systems, June 57, 1985, Kyoto, Japan, pp. 14151418.
 Larson, L., Jensen, J., Greiling, P., and Temes, G.C., “GaAs Differential Amplifiers,” Techn. Digest of the GaAs IC Symp., November 1214, 1985, Monterey, CA, pp. 1922.
 Robert, J., Temes, G.C., Krummenacher, F., Valencic, V., and Deval, P., “A LowVoltage HighResolution CMOS A/D Converter with Analog Compensation,” Proc. of IEEE 1986 Custom IC Circuits Conf., May 986, Rochester, NY, pp. 362365.
 Haug, K., Maloberti, F., and Temes, G.C., “SwitchedCapacitor Circuits with Low OpAmp Gain Sensitivity,” Proc. 1986 IEEE International Symp. on Circuits and Systems, May 1986, San Jose, CA, pp. 797800.
 Robert, J., Temes, G.C., Krummenacher, F., Valencic, V., and Deval, P., “Offset and Clock Feedthrough Compensated SC Integrators,” Proc. 1986 IEEE International Symp. on Circuits and Systems, May 1986, San Jose, CA, pp. 817818.
 Babanezhad, J.N. and Temes, G.C., “Analog MOS Computational Circuits,” Proc. 1986 IEEE International Symp. on Circuits and Systems, May 1986, San Jose, CA, pp. 11571160.
 Larson, L.E., Martin, K., and Temes, G.C., “GaAs SwitchedCapacitor Circuits for Video Signal Processing,” Digest of 1987 IEEE International SolidState Circuits Conf., New February 1987, York, pp. 4041 and 332.
 Larson, L.E. and Temes, G.C., “SwitchedCapacitorBuilding Blocks with Reduced Sensitivity to Finite Amplifier Gain, Bandwidth and Offset Voltage,” Proc. of 1987 IEEE International Symp. on Circuits and Systems, May 1987, Philadelphia, PA, pp. 334338.
 Larson, L.E., Temes, G.C., and Martin, K.W., “SwitchedCapacitor Circuits with Reduced Sensitivity to Finite Amplifier Gain, Bandwidth and Offset Voltage,” Proc. of European Conf. on Circuit Theory and Design, September 1987, Paris, France, pp. 543548.
 Wang, F.J. and Temes, G.C., “A Fast OffsetFree SampleandHold Circuit,” Proc. of IEEE Custom Integrated Circuits Conf., May 1619, 1988, Rochester, NY, pp. 5.6.15.6.3.
 Wang, F.J., Temes, G.C., and Law, S., “A QuasiPassive CMOS Pipeline D/A/ Converter,” Proc. of IEEE Custom Integrated Circuits Conf., May 1619, 1988, Rochester, NY, pp. 18.1.118.1.4.
 Temes, G.C., Martin, K., and Larson, L., “StateoftheArt and Future Prospects for Analog Signal Processing,” Proc. of the IEEE International Symp. on Circuits and Systems, June 79, 1988, Espoo, Finland, pp. 16551660.
 Temes, G.C., Wang, F.J., and Watanabe, K., “Novel Pipelined Data Converters,” Proc. of the IEEE International Symp. on Circuits and Systems, June 79, 1988, Espoo, Finland, pp. 19431946.
 Watanabe, K., Temes, G.C., and Moriuchi, Y., “A New DigitaltoAnalog Conversion Algorithm,” Proc. of the IEEE International Symp. on Circuits and Systems, June 79, 1988, Espoo, Finland, pp. 28172820.
 Cataltepe, T., Kramer, A., Larson, L., Temes, G.C., and Walden, R., “Digitally Corrected MultiBit ΣΔ Data Converters,” Proc. of the IEEE International Symp. on Circuits and Systems, May 811, 1989, Portland, OR, pp. 647650.
 Candy, J.C. and Temes, G.C., “Tutorial Discussion of the Oversampling Method for A/D and D/A Conversion,” Proc. of the International Symp. on Circuits and Systems Conf., May 13, 1990, New Orleans, LA, pp. 910913.
 Walden, R.H., Cataltepe, T., and Temes, G.C., “Architectures for HighOrder Multibit ΣΔ Modulators,” Proc. of the International Symp. on Circuits and Systems, May 13, 1990, New Orleans, LA, pp. 895898.
 Hadidi, K., Temes, G.C., and Martin, K.W., “Error Analysis and Digital Correction Algorithms for Pipelined A/D Converters,” Proc. of the International Symp. on Circuits and Systems, May 13, 1990, New Orleans, LA, pp. 17091712.
 Ki, W.H. and Temes, G.C., “OffsetCompensated SwitchedCapacitor Integrators,” Proc. of the International Symp. on Circuits and Systems, May 13, 1990, New Orleans, LA, pp. 28292832.
 Hadidi, K., Tso, V.S., and Temes, G.C., “Fast SuccessiveApproximation A/D Converters,” Proc. of the Custom Int. Circuits Conf., May 1316, Boston, MA, 1990, pp. 6.1.16.1.4.
 Comino, V., Steyaert, M., and Temes, G.C., “A FirstOrder CurrentSteering SigmaDelta Modulator,” Proc. of the Custom Int. Circuits Conf., May 1316, 1990, Boston, MA, pp. 6.3.16.3.4.
 Candy, J.C. and Temes, G.C., “Oversampling Methods for Data Conversion,” Proceedings, IEEE Pacific Rim Conf. on Communications, Computers, and Signal Processing, Victoria, B.C., Canada, May 910, 1991, pp. 498502.
 Liu, C.T., Samueli, H., and Temes, G.C., “FIR Filter Design for SigmaDelta A/D Converters Using Quadratic Programming,” Proceedings, IEEE Pacific Rim Conf. on Communications, Computers, and Signal Processing, pp. 760763.
 Powell, S.R., Chan, P.M., and Temes, G.C., “A Ripple Reduction Technique for Digital Filters,” Proceedings, 1991 IEEE Internat. Symp. on Circuits and Systems, Singapore, June 1114, 1991, pp. 148151.
 Liu, C.T., Samueli, H., and Temes, G.C., “FIR Filter Design Using Quadratic Programming,” Proceedings, 1991 IEEE Internat. Symp. on Circuits and Systems, Singapore, June 1114, 1991, pp. 148151.
 Ki, W.H. and Temes, G.C., “Gain and Offset Compensated SwitchedCapacitor Filters,” Proceedings, 1991 IEEE Internat. Symp. on Circuits and Systems, Singapore, June 1114, 1991, pp. 15611564.
 Vital, J.C. and Temes, G.C., “Clock Generation System with Reduced Filter Noise in the Baseband,” Proceedings, 1991 IEEE Internat. Symp. on Circuits and Systems, Singapore, June 1114, 1991, pp. 26212624.
 Hadidi, Kh. and Temes, G.C., “A HighResolution LowOffset and HighSpeed Comparator,” Proceedings, Custom Int. Circuits Conf., May 36, 1992, Boston, MA, pp. 16.1.116.1.4.
 SarhangNejad, M. and Temes, G.C., “A True 16bit 20 kHz Multibit ΣΔ ADC with Digital Correction,” Proceedings, Custom Int. Circuits Conf., May 36, 1992, Boston, MA, pp. 16.4.116.4.4.
 Czarnul, Z., Temes, G.C., Yesilyurt, A.G., and Zhang, Z., “Bandpass DeltaSigma A/D Converters with PseudoNPath SC Integrators,” Proceedings, International Symp. on Circuits and Systems, May 1013, 1992, San Diego, CA, pp. 593596.
 Xu, X.F. and Temes, G.C., “The Implementation of DualTruncation ΣΔ D/A Converters, Proceedings, International Symp. on Circuits and Systems, May 1013, 1992, San Diego, CA, pp. 597600.
 Ki, W.H. and Temes, G. C., “AreaEfficient Gain and OffsetCompensated Very Large Time Constant SC Biquads,” Proceedings, International Symp. on Circuits and Systems, May 1013, 1992, San Diego, CA, pp. 11871190.
 Czarnul, Z., Yesilyurt, A.G., and Temes, G.C., “Multiplexed Noise Shaping Structures for DeltaSigma Modulators,” Proceedings, International Symp. on Circuits and Systems, May 1013, 1992, San Diego, CA, pp. 13081311.
 Rangan, G., Kenney, J.G., Ramamurthy, K., and Temes, G.C., “HighSpeed Buffers for OpAmp Characterization,” Proceedings, International Symp. on Circuits and Systems, May 36, 1993, Chicago, IL, pp. 994997.
 Abdennadher, S., Kiaei, S., Yang, Y., and Temes, G.C., “Adaptive Digital Correction for DualQuantization ΔΣ Modulators,” Proceedings, International Symp. on Circuits and Systems, May 36, 1993, Chicago, IL, pp. 12281230.
 Temes, G.C., Deval, P., and Valencic, V., “SC Circuits: The State of the Art Compared to SI Techniques,” Proceedings, International Symp. on Circuits and Systems, May 36, 1993, Chicago, IL, pp. 12311234.
 Temes, G.C., “SigmaDelta Data Converter Architectures with Multibit Internal Quantizers,” Proceedings, European Conf. on Circuit Theory and Design, August 30September 3, 1993, Davos, Switzerland.
 Hadidi, K. and Temes, G.C., “A Novel Input Differential Pair for Improved Linearity Buffer and S/H Amplifier Design,” Proceedings, IEEE International Symp. on Circuits and Systems, London, UK, May 30June 2, 1994, pp. 9396.
 Goes, J., Franca, J., Paulino, N., Grilo, J., and Temes, G.C., “HighLinearity Calibration of LowResolution D/A Converters,” Proceedings, IEEE International Symp. on Circuits and Systems, London, UK, May 30June 2, 1994, pp. 345348.
 Hairapetian, A. and Temes, G.C., “A DualQuantization MultiBit SigmaDelta A/D Converter,” Proceedings, IEEE International Symp. on Circuits and Systems, London, UK, May 30June 2, 1994, pp. 437440.
 Yoshizawa, H. and Temes, G.C., “HighLinearity SwitchedCapacitor Circuits in Digital CMOS Technology,” Proceedings, IEEE International Symp. on Circuits and Systems, Seattle, WA, April 30May 3, 1995, pp. 10291032.
 Cao, Y. and Temes, G.C., “CMOS Circuits for OnChip Capacitance Ratio Testing on Sensor Readout,” Proceedings, IEEE International Symp. on Circuits and Systems, Seattle, WA, April 30May 3, 1995, pp. 18481851.
 Grilo, J., McRobbie, E., Halim, R., and Temes, G.C., “A 1.8 V 94 dB Dynamic Range DeltaSigma Modulator for Voice Applications,” Digest, IEEE International SolidState Circuits Conference, San Francisco, CA, February 810, 1996, pp. 230231 and 451.
 Huang, Y., Temes, G.C., and Ferguson, P., “Novel HighFrequency T/H Stages with Offset and Gain Compensation,” Proceedings, IEEE International Symposium on Circuits and Systems, Atlanta, GA, May 1215, 1996, pp. 155158.
 Huang, Y., Temes, G.C., and Ferguson, P., “Reduced Nonlinear Distortion in Circuits with Correlated Double Sampling,” Proceedings, IEEE International Symposium on Circuits and Systems, Atlanta, GA, May 1215, 1996, pp. 159162.
 Cauwenberghs, G. and Temes, G.C., “Adaptive Calibration of Multibit Quantization Oversampled A/D Converters,” Proceedings, IEEE International Symposium on Circuits and Systems, Atlanta, GA, May 1215, 1996, pp. 512515.
 Wang, B., Sun, T., Cao, Y., and Temes, G.C., “HighAccuracy Circuits for OnChip Capacitive Ratio Testing and Sensor Readout,” Proceedings, IEEE International Workshop on Emergent Technologies for Instrumentation and Measurements, Como, Italy, June 1011, 1996, pp. 6875.
 Yoshizawa, H., Temes, G.C., Ferguson, P., and Krummenacher, F., “Novel Design Techniques for HighLinearity MOSFETOnly SC Circuits,” Digest, 1996 Symposium on VLSI Circuits, Honolulu, HI, June 1315, 1996, pp. 152153.
 Wiesbauer, A. and Temes, G.C., “OnLine Digital Compensation of Analog Circuit Imperfections for Cascaded DeltaSigma Modulators,” IEEECAS Workshop on Analog and Mixed IC Design, Pavia, Italy, September 1314, 1996, pp. 9297.
 Wiesbauer, A. and Temes, G.C., “Adaptive Compensation of Analog Circuit Imperfections for Cascaded DeltaSigma Modulators,” Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, November 36, 1996.
 Temes, G.C., “An Overview of NyquistRate and Oversampled Data Converters in Telecommunications,” Keynote Address, Actas I. Conferencia Nacional de Telecomunicacoes, Aveiro, Portugal, April 1011, 1997, pp. 1518.
 Huang, Y., Temes, G.C., and Yoshizawa, H., “A HighLinearity LowVoltage AllMOSFET DeltaSigma Modulator,” Proceedings, IEEE Custom Integrated Circuits Conf., Santa Clara, CA, May 58, 1997, pp. 293296.
 Wang, Bo, Kajita, T., Sun, T., and Temes, G.C., “HighAccuracy Circuits for OnChip Capacitive Ratio Testing and Sensor Readout,” Proceedings, IEEE Instrumentation and Measurement Techn. Conf., Ottawa, Canada, May 1921, 1997, pp. 11691172.
 Yoshizawa, H., Huang, Y., and Temes, G.C., “MOSFETOnly SwitchedCapacitor Circuits in Digital CMOS Technologies,” Proceedings, IEEE Internat. Symp. on Circuits and Systems, Hong Kong, June 912, 1997, pp. 457460.
 Grilo, J., Huang, Y., and Temes, G.C., “The Realization of DeltaSigma A/D Converters in LowVoltage Digital CMOS Technology,” Proceedings, IEEE Midwest Symp. on Circuits and Systems, August 36, 1997.
 Kovacs, J. and Temes, G.C., “Analog CMOS ICs in Communication and Mass Storage Applications,” European Conf. on Circuit Theory and Design, Budapest, Hungary, August 31September 3, 1997.
 Huang, Y., Temes, G.C., and Ferguson, P., “Experimental Results on Reduced Harmonic Distortion in Circuits with Correlated Double Sampling,” Digest, 1998 IEEE Symp. on VLSI Circuits, Honolulu, HI, June 911, 1998, pp. 224227.
 Sun, T., Wiesbauer, A., and Temes, G.C., “Adaptive Compensation of Analog Circuit Imperfections for Cascaded DeltaSigma ADCs,” Proceedings, 1998 IEEE International Symp. on Circuits and Systems, Vol. I, Monterey, CA, May 31June 3, 1998, pp. 405407.
 Wang, B., Kajita, T., Sun, T., and Temes, G.C., “New HighPrecision Circuits for OnChip Capacitor Ratio Testing and Sensor Readout,” Proceedings, 1998 IEEE International. Symp. on Circuits and Systems, Vol. I, Monterey, CA, May 31June 3, 1998, pp. 547550.
 Grilo, J.A. and Temes, G.C., “Predictive Correlated Double Sampling SwitchedCapacitor Integrators,” Proceedings, 1998 IEEE International Conf. on Electronics, Circuits and Systems, Lisboa, Portugal, September 710, 1998, pp. 2.92.12.
 Huang, Y., Temes, G.C., and Ferguson, P., “Offset and GainCompensated TrackandHold Stages,” Proceedings, 1998 IEEE International Conf. on Electronics, Circuits and Systems, Lisboa, Portugal, September 710, 1998, pp. 2.132.16.
 Grilo, J. and Temes, G.C., “The Use of Predictive Correlated Double Sampling Techniques in LowVoltage DeltaSigma Modulators,” Proceedings, 1998 IEEE International Conf. on Electronics, Circuits and Systems, Lisboa, Portugal, September 710, 1998, pp. 2.1492.152.
 Temes, G.C., “Oversampling A/D and D/A Converters,” invited paper, IX European Signal Processing Conf., Rhodes, Greece, September 811, 1998.
 Sun, T., Wiesbauer, A., and Temes, G.C., “Adaptive Compensation of Analog Circuit Imperfections for Cascaded DeltaSigma ADCs,” Proceedings, 24th European SolidState Circuits Conf., The Hague, Netherlands, September 2224, 1998.
 Temes, G.C., “DeltaSigma Data Converters: The StateoftheArt and Future Trends,” invited presentation, Proceedings, NASA Symp. on VLSI Design, Albuquerque, NM, October 12, 1998, p. 6.1.
 Temes, G.C., “HighLinearity SwitchedCapacitor Circuits Using MOSFET GateChannel Capacitors,” invited plenary lecture, Proceedings, XIII Design of Circuits and Integrated Systems Conf., Madrid, Spain, Nov. 1720, 1998, pp. XXI.
 Steensgaard, J., Moon, U. and Temes, G.C., “MismatchShaped PseudoPassive TwoCapacitor DAC,” Proceedings, IEEE Alessandro Volta Workshop on LowVoltage Design, Como, Italy, March 45, 1999, pp. 144152.
 Steensgaard, J., Moon, U., and Temes, G.C., “MismatchShaping Serial DigitaltoAnalog Converter,” Proceedings, IEEE Int. Symp. Circuits and Systems, vol. II, May 30June 2, 1999, pp. 58.
 Bidari, E., Keskin, M., Maloberti, F., Moon, U., Steensgaard, J., and Temes, G., “LowVoltage SwitchedCapacitor Circuits,” Proceedings, IEEE Int. Symp. Circuits and Syst., vol. II, May 30June 2, 1999, pp. 4952.
 Zheng, Z., Moon, U., Steensgaard, J., Wang, B., and Temes, G., “Capacitor Mismatch Error Cancellation Technique for a SuccessiveApproximation A/D Converter,” Proceedings, IEEE Int. Symp. Circuits and Syst., vol. II, May 30June 2, 1999, pp. 326329.
 Temes, G.C., “Accurate Linear Analog Signal Processing and Data Conversion Using Inaccurate Nonlinear Components,” Keynote address, 42nd IEEE Midwest Circuit Symp., Las Cruces, NM, August 811, 1999.
 Wang, B. and Temes, G.C., “Novel CMFB Circuits for Stages with Large CommonMode Input,” Proceedings, European Conf. on Circuit Theory and Design, Stresa, Italy, vol. I, August 29September 2, 1999, pp. 912.
 Temes, G., Moon, U., and Steensgaard, J., “Analog (S)witchcraft, or How to Perform Accurate and Linear Data Conversion Using Inaccurate Nonlinear Elements,” Plenary lecture, IEEE Elec. Circuits Syst. Conf., Bratislava, Slovakia, September 68, 1999, pp. 97101.
 Moon, U., Temes, G., Bidari, E., Keskin, M., Wu, L., Steensgaard, J., and Maloberti, F., “SwitchedCapacitor Circuit Techniques in Submicron LowVoltage CMOS,” IEEE Int. Conf. VLSI CAD, Seoul, Korea, October 1999, pp. 349358.
 Ferguson, P., Haurie, X. and Temes, G.C., “A Highly Linear LowPower 10Bit DAC for GSM,” Proceedings, IEEE Custom Integrated Circuits Conf., Orlando, FL, May 2124, 2000.
 Zheng, Z., Min, B., Moon, U., and Temes, G., “Efficient ErrorCancelling Algorithmic ADC,” Proceedings, IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 2831, 2000.
 Kiss, P., Silva, J., Moon, U., Stonick, J., and Temes, G., “Improved Adaptive Digital Compensation for Cascaded DeltaSigma ADCs,” Proceedings, IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 2831, 2000, pp. 3336.
 Kajita, T., Moon, U., and Temes, G., “A NoiseShaping Accelerometer Interface Circuit for TwoChip Implementation,” Proceedings, IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 2831, 2000, pp. 337340.
 Moon, U., Silva, J., Steensgaard, J., and Temes, G., “A SwitchedCapacitor DAC with Analog Mismatch Correction,” Proceedings, IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 2831, 2000, pp. 421424.
 Wu, L., Keskin, M., Moon, U., and Temes, G., “Efficient CommonMode Feedback Circuits for PseudoDifferential SwitchedCapacitor Stages,” Proceedings, IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 2831, 2000, pp. 445448.
 Keskin, M., Moon, U., and Temes, G., “LowVoltage SwitchedCapacitor Resonators,” IEEE Dallas Workshop Low Power/Voltage Circuits Syst., March 2001, pp. 1922.
 Kajita, T., Moon, U., and Temes, G., “A NoiseShaping Accelerometer Interface Circuit for TwoChip Implementation,” Proceedings, IEEE Inst. Meas. Technology Conf., BudapestHungary, May 2001, pp. 15811586.
 Kiss, P., Moon, U., Steensgaard, J., Stonick, J., and Temes, G., “Multibit DS ADC with MixedMode DAC Error Correction,” Proceedings, IEEE Int. Symp. Circuits Syst., May 2001, pp. 280283.
 Keskin, M., Moon, U., and Temes, G., “LowVoltage LowSensitivity SwitchedCapacitor Bandpass DS Modulator,” Proceedings, IEEE Int. Symp. Circuits Syst., May 2001, pp. 348351.
 Perigny, R., Moon, U., and Temes, G., “Area Efficient CMOS Charge Pump Circuits,” Proceedings, IEEE Int. Symp. Circuits Syst., May 2001, pp. 492495.
 Keskin, M., Moon, U., and Temes, G., “A 1V, 10 MHz Clock Rate, 13Bit ΔΣ Modulator Using UnityGainReset Op Amps,” Proceedings, European SolidState Circuits Conf., Villach, Austria, September 2001, pp. 532535.
 Silva, J., Wang, X., Kiss, P., Moon, U., and Temes, G.C., “Digital Techniques for Improved DeltaSigma Data Conversion,” Invited Paper, Proceedings, IEEE Custom Integrated Circuits Conf., May 2002, pp. 183186.
 Wang, X., Moon, U., Liu, M., and Temes, G.C., “Digital Correlation Technique for the Estimation and Correction of DAC Errors in Multibit MASH DeltaSigma ADCs,” Proceedings, IEEE Int. Symp. Circuits Syst., Phoenix, AZ, May 2002, vol. IV, pp. 691694.
 Rao, A., McIntyre, W., Parry, J., Moon, U., and Temes, G.C., “BuckBoostSC DCDC Voltage Regulator Using DeltaSigma Control Loop,” Proceedings, IEEE Int. Symp. Circuits Syst., Phoenix, AZ, May 2002, vol. IV, pp. 743746.
 X. Wang, Kiss, P., Moon, U., and Temes, G.C., “Digital Correlation Technique for the Estimation and Correction of DAC Errors in Multibit MASH DeltaSigma ADCs,” Proceedings, Int. Conf. on Advanced A/D & D/A Techn., Prague, Czech Rep., June 2002.
 M. Keskin, M. Brown, Moon, U., and Temes, G.C., “A VoltageMode SC Bandpass DeltaSigma Modulator,” Proceedings, Int. Conf. on Advanced A/D & D/A Techn., Prague, Czech Rep., June 2002.
 Markus, J. and Temes, G.C., “An Efficient SigmaDelta NoiseShaping Architecture for WideBand Applications,” Proceedings, Int. Conf. on Advanced A/D & D/A Techn., Prague, Czech Rep., June 2002.
 Rao, A., McIntyre, W., Moon, U., and Temes, G.C., “A Noiseshaped SC DCDC Voltage Regulator,” Proceedings, ESSCIRC Dig. Tech. Papers, Florence, Italy, September 2224, 2002, pp. 375378.
 Bruneau, D., Early, A., Moon, U., and Temes, G.C., “HighSpeed SwitchedCapacitor Filters Based on the UnityGain Buffer,” IEEJ Analog VLSI Workshop, September 2002, pp. 59.
 Keskin, M., Moon, U., and Temes, G.C., “A 0.9V 10.7MHz 3.6 mW Bandpass ΔΣ Modulator Using UnityGainReset Opamps,” Proceedings, IEEE Int. Workshop ADC Mod. Test., September 2003.
 Keskin, M., Moon, U., and Temes, C., “Amplifier Imperfection Effects in SwitchedCapacitor Resonators,” Proceedings, IEEE Int. Workshop ADC Mod. Test., September 2003.
 Markus, J., Silva, J., and Temes, G.C., “Design Theory for HighOrder Incremental Converters,” Proceedings, IEEE Internat. Symp. on Intelligent Signal Processing (WISP/2003), Budapest, Hungary, September 2003.
 Dai, S., von Jouanne, A., Wallace A., and Temes, G.C., “DeltaSigma Modulation Applications in NeutralPoint Clamped Inverters,” Proceedings, IAS2003, Salt Lake City, October 2003.
 Ceballos, J. and Temes, G.C., “Some Techniques to Improve the Performance of DeltaSigma Modulators,” X. IBERCHIP Workshop, Cartagena de Indias, Columbia, March 1012 2004.
 Xiao, Y., Moon, U. and Temes, G., "A Tunable DutyCycleControlled SwitchedRMOSFETC Filter for LowVoltage and HighLinearity Applications," Proc. IEEE Internat. Symp. on Circuits and Systems, Vancouver, Canada, vol. I, pp. 433436, May 2326, 2004.
 Silva, J., Moon, U. and Temes, G., "LowDistortion DeltaSigma Topologies for MASH Architectures," Proc. IEEE Internat. Symp. on Circuits and Systems, Vancouver, Canada, vol. I, pp.11441147, May 2326, 2004.
 Ceballos, J. Steensgaard, J. and Temes, G., "A Digital Correction Scheme for Multibit DeltaSigma D/A Converters," 11th Electronic Devices and Systems Conference, Czech Republic, Sept. 9 10, 2004.
 Wang, X., Guo, Y., Moon, U. and Temes, G., "Experimental Verification of a CorrelationBased Correction Algorithm for MultiBit DeltaSigma ADCs," IEEE Custom Integrated Circuits Conf., pp. 523526, Oct. 2004.
 Han, J., von Jouanne, A. and Temes, G., "A New Approach to Reducing Output Ripple in SwitchedCapacitorBased StepDown DC/DC Converters," IEEE IAS 39th Annual Meeting, Oct. 2004, Vol. 2, pp.11151120.
 Ahn, G., Chang, D., Brown, M., Ozaki, N., Youra, H., Yamamura, K., Hamashita, K., Temes, G. and Moon, U., "A 0.6 V 82 dB DeltaSigma Audio ADC Using SwitchedRC Integrators," IEEE Internat. SolidState Circuits Conf. Digest, 48, Febr. 610, 2005, pp. 166167.
 Han, J., von Jouanne, A. and Temes, G., "Design and IC Implementation of an UltraLowRipple SwitchedCapacitorBased Buck DCDC Converter," Applied Power Electronics Conference and Exposition, March 610, 2005, Austin, TX, Vol. 3, pp.14471452.
 Ceballos, J. and Temes, G., "Improved Current Cells for CurrentSteering DigitaltoAnalog Converters," XI IBERCHIP WORKSHOP, March 2005, Salvador de BahiaBrasil.
 Ceballos, J., Steensgaard, J. and Temes, G., "Digital Correction for Multibit D/A Converters,” XI IBERCHIP WORKSHOP, March 2005, Salvador de BahiaBrasil.
 Rengachari, T., Sharma, V. Temes, G. and Moon, U., “A 10Bit Algorithmic A/D Converter for Cytosensor Application," Proc. IEEE Internat. Symp. on Circuits and Sys., May 2326, 2005, Kobe, Japan.
 Sharma, V., Moon, U. and Temes, G., “A Generic Multilevel Multiplying D/A Converter for Pipeline ADCs,” Proc. IEEE Internat. Symp. on Circuits and Sys., May 2326, 2005, Kobe, Japan.
 Steensgaard, J., Zhang, Z. and Temes, G., “DualPath DeltaSigma Modulators,” IEEE Int. Midwest Symp. on Circuits and Symp., Cincinnati, Aug. 710, 2005.
 Ceballos, J., Galton, I. and Temes, G., “Stochastic AnalogtoDigital Conversion,” IEEE Int. Midwest Symp. on Circuits and Symp., Cincinnati, Aug. 710, 2005.
 Quiquempoix, V., Deval, Ph., Barreto, A., Bellini, G., Collings, J., Markus, J., Silva, J. and Temes, G., “A LowPower 22Bit Incremental ADC with 4 ppm INL, 2 ppm Gain Error and 2 uV DC Offset,” IEEE European SolidState Circuits Conference Sept. 1216, 2005.
 Ahn G., P. Hanumolu, M. Kim, S. Takeuchi, T. Sugimoto, K. Hamashita,, Takeuchi, S., Temes, G.C. and Moon, U., “A 12b 10MS/s Pipelined ADC Using Reference Scaling,” IEEE Symp. on VLSI Circuits, pp. 220221, June 2006.
 Kim, M.G., Ahn, G.C., Hanumolu, P.K., Lee, S., Kim, S., You, J., Temes, G. and Moon, U., “A 0.9V 92dB DoubleSampled SwitchedRC DeltaSigma Audio ADC,” IEEE Symp. on VLSI Circuits, pp. 160161, June 2006.
 Meng, Q., Lee, K., Sugimoto, T., Hamashita, K., Takasuka, K., Takeuchi, S., Moon, U. and Temes, G., “A 0.8V, 88dB DualChannel Audio DeltaSigma DAC with Headphone Driver,” IEEE Symp. on VLSI Circuits, pp. 5354, June 2006.
 Yoshizawa, H. and Temes, G., “SwitchedCapacitor TrackandHold Amplifier with Low Sensitivity to OpAmp Imperfections,” Proc. IEEE Int. Symp. on Circuits and Sys., May 2006.
 Markus, J., Deval, Ph., Quiquempoix, V., Silva, J. and Temes, G., “Incremental DeltaSigma Structures for DC Measurement: An Overview,” IEEE Custom IC Conf. 2006, Invited Paper, pp. 4148, Sept. 2006.
 Kurahashi, P., Hanumolu, P., Temes, G. and Moon, U., “A 0.6V Highly Linear SwitchedRMOSFETC Filter,” IEEE Custom IC Conf. 2006, Best Student Paper award, pp. 833836, Sept. 2006.
 Lee, K. and Temes, G.C., “Enhanced SplitArchitecture DeltaSigma ADC,” Internat. Conf. on Electronics, Circuits and Systems, Nice, France, Dec. 1013, 2006.
 Sharma, V. Moon, U. and Temes, G.C., “Efficient Pipelined ADCs Using IntegerGain MDACs,” IEEE Conf. on PhD Research in Microelectronics, Bordeaux, France, July 25, 2007.
 Lee, K., Temes, G.C. and Maloberti, F., “NoiseCoupled MultiCell DeltaSigma ADCs,” IEEE Internat. Symp. On Circuits and Systems, New Orleans, LA, pp. 249252, May 2730, 2007.
 Zhang, Zh. and Temes, G.C., “A Segmented DataWeighted Averaging Technique,” IEEE Internat. Symp. On Circuits and Systems, New Orleans, LA, pp. 481484, May 2730, 2007.
 Yoshizawa, H. and Temes, G.C., “Predictive SwitchedCapacitor Trackand Hold Amplifier with Improved Linearity,” IEEE Internat. Symp. On Circuits and Systems, New Orleans, LA, pp. 233236, May 2730, 2007.
 Maghari, N., Kwon, S., Temes, G.C. and Moon, U., “MixedOrder Sturdy MASH DeltaSigma Modulator,” IEEE Internat. Symp. On Circuits and Systems, New Orleans, LA, pp. 257260, May 2730, 2007.
 Zhang, Zh., Steensgaard, J., Temes, G.C. and Wu, J., “A Split 20 MASH with Dual Digital Error Correction,” IEEE Symp. on VLSI Circuits, Kyoto, Japan, pp. 242243, June 1416, 2007.
 Zhang, Zh., Yu, W., Lucchese, L. Kim, D. and Temes, G.C., “Multiplexed Incremental ADCs,” IEEE Midwest Symp. on Circuits and Systems, Montreal, Canada, Aug. 58, 2007.
 Chen, X., Wang, Y., Fujimoto, Y., Lo Re, P., Kanazawa, Y., Steensgaard, J. and Temes, G.C., “A 18mW CT DS Modulator with 25MHz Bandwidth for Next Generation Wireless Applications,” IEEE Custom IC Conf. Digest, pp. 7376, Sept. 2007.
 Lee, K., Chae, J, Aniya, M., Hamashita, K., Takasuka, K., Takeuchi. S. and Temes, G.C., “A NoiseCoupled TimeInterleaved DS ADC with 4.2MHz, BW, 98dB THD and 79dB SNDR,”IEEE Internat. SolidState Circuits Conf., pp. 1214, Febr. 2008.
 Lee, K. and Temes, G.C., “Efficient FullyFloating DoubleSampling Integrator for DeltaSigma ADCs,” 2008 IEEE Internat. Symp. On Circuits and Systems, pp.14401443, May 2008.
 Wang, Y., Lee, K. and Temes, G.C., “A 2.5 MHz BW and 78 dB SNDR DeltaSigma Modulator Using Dynamically Biased Amplifiers,” IEEE Custom IC Conf. Digest, pp. 97100, Sept. 2008.
 Lee. K., Miller, M. and Temes, G.C., “An 8.1 mW, 82 dB DeltaSigma ADC with 1.9 MHz BW and 98 dB THD,” IEEE Custom IC Conf. Digest, pp. 9396, Sept. 2008.
 Temes, G.C., “New Architectures for LowPower DeltaSigma ADCs,” Keynote Address, IEEE Asia Pacific Conf. on Circuits and Systems, Dec. 2008.
 Nishida, Y. and Temes, G.C., “An Enhanced DualPath DeltaSigma ADC,” 2009 IEEE Internat. Symp. on Circuits and Systems, pp. 13331336, May 2009.
 Yu, W. and Temes, G.C. “A Digital Calibration Technique for DAC Mismatches in DeltaSigma Modulators,” 2009 IEEE Internat. Symp. on Circuits and Systems, pp. 13371340, May 2009.
 Lee, K. and Temes, G.C.,”Improved LowDistortion DeltaSigma ADC Topology,” 2009 IEEE Internat. Symp. on Circuits and Systems, pp. 13411344, May 2009.
 Shen, W. and Temes, G.C., “DoubleSampled DeltaSigma Modulator with Relaxed Feedback Timing,” Midwest Symp. on Circuits and Systems, pp. 9396, Aug. 25, 2009.
 Wang, Y. and Temes, G.C., “DeltaSigma ADCs with SecondOrder Noise Shaping Enhancement,” Midwest Symp. on Circuits and Systems, pp. 345348, Aug. 25, 2009.
 Wang, Y. and Temes, G.C., “NoiseCoupled ContinuousTime DeltaSigma ADCs,” Midwest Symp. on Circuits and Systems, pp. 341344, Aug. 25, 2009.
 Wang, Y. and Temes, G.C., “Wideband DeltaSigma ADCs Using DirectChargeTransfer Adder,” Midwest Symp. on Circuits and Systems, pp. 9396, Aug. 25, 2009.
 Wang, Y. and Temes, G.C., “LowDistortion DoubleSampling DeltaSigma ADC Using a DirectChargeTransfer Adder,” IEEE SOOC Conf., pp. 7174, Sept. 911, 2009.
 Lee, K. and Temes, G.C., “NoiseCoupled DeltaSigma Data Converters,” AACD 2010, Graz, Austria, March 2325, 2010.
 Cao, J. and Temes, G.C., “RadixBased Digital Correction Technique for TwoCapacitor DACs,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 565568, June 2010.
 Yu, W., Lin, j. and Temes, G.C., “TwoStep JunctionSplitting SAR AnalogtoDigital Converter,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 14481451, June 2010.
 Lin, J., Yu, W. and Temes, G.C., “EnergyEfficient TimeInterleaved and Pipelined SAR ADCs,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 14521455, June 2010.
 Wang, Y. and Temes, G.C., “Design Techniques for DiscreteTime DeltaSigma ADCs with Extra Loop Delay,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 21592162, June 2010.
 Zanbaghi, R., Fiez, T. And Temes, G.C., “A New ZeroOptimization Scheme for NoiseCoupled DeltaSigma ADCs,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 21632166, June 2010.
 Wang, T. and Temes, G.C., “SwitchedResistor Tuning Techniques for Higly Linear GmC Filter Design,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 36173620, June, 2010.
 Wang, Y., Chen, Ch., Yu, W. and Temes, G.C., “NoiseCoupled LowPower Incremental ADCs,” 2010 IEEE Internat. Symp. on Circuits and Systems, pp. 40014004, June, 2010.
 Wang, T. and Temes, G.C., “LowPower SwitchedCapacitor Integrator for DeltaSigma ADCs,” Internat. Midwest Symp. on Circuits and Systems, pp. 493496, Aug. 2010.
 Zanbaghi, R. and Temes, G.C., “An OpAmp Sharing Technique for ContinuousTime DeltaSigma Modulators,” IEEE Internat. Midwest Symp. on Circuits and Systems, pp. 592595, Aug. 2010.
 Shen, W., Wang, T. and Temes, G.C., “LowDistortion DeltaSigma Modulator Employing Modified ChargePump Based SwitchedCapacitor Integrator,” IEEE Internat. Midwest Symp. on Circuits and Systems, pp. 901904, Aug. 2010.
 Yu, W., Aslan, M. and Temes, G.C., “82dB SNDR 20Channel Incremental ADC with Optimal Decimation Filter and Digital Correction,” IEEE Custom Integrated Circuits Conf., pp. 14, Sept. 21, 2010.
 Chae, J., Lee, S., Anija, M., Takeuchi, S., Hamashita, K. Hanumolu, P. and Temes, G.C., “A 63 dB, 16 mW, 20 MHz BW DoubleSampled ADC with an EmbeddedAdder Quantizer,” IEEE Custom Integrated Circuits Conf., pp. 14, Sept. 21, 2010.
 Lee, S. et al, “A DoubleSampled LowDistortion Cascade ΔΣ Modulator with an Adder/Integrator for WLAN Application,” IEEE Custom Integrated Circuits Conf., San Jose, CA, Sept. 18 – 21, 2011.
 Zanbaghi, R., Saxena, S., Temes, G.C. and Fiez, T.S., “A 75 dB SNDR, 10 MHz Conversion Bandwidth StageShared 22 Mash ΔΣ Modulator Dissipating 9 mW,” IEEE Custom Integrated Circuits Conf., San Jose, CA, Sept. 18 – 21, 2011.
 Li, Wei and Temes, G.C., “Digital Foreground Calibration Methods for SAR ADCs,” IEEE Internat. Circuits and Systems Symp., pp. 10541057, May 2023, 2012, Seoul, Korea.
 Chen, C.H., Crop, J., Chae, J., Chiang, P. and Temes, G.C., “A 12Bit, 7 uW/Channel, 1 kHz/Channel Incremental ADC for Biosensor Interface Circuits,” IEEE Internat. Circuits and Systems Symp., May 2023, 2012, pp. 2969 – 2972, Seoul, Korea.
 Cao, J., Raich, R., Cauwenberghs, G. and Temes, G.C., “MultiChannel MixedSignal Noise Source with Applications to Stochastic Equalization,” IEEE Internat. Circuits and Systems Symp., pp. 24972500, May 2023, 2012, Seoul, Korea.
 Tong, T. and Temes, G.C., “Calibration Technique for SAR AnalogtoDigital Converters,” IEEE Internat. Circuits and Systems Symp., pp. 29932996, May 2023, 2012, Seoul, Korea
 Wang, T., Li, W., Yoshizawa, H., Aslan, M. and Temes, G.C., “A 101dB DR 1.1mW Audio ΔΣ Modulator with DirectChargeTransfer Adder and Noise Shaping Enhancement,” IEEE Asian SolidState Circuits Conf., Nov. 1214, 2012, Kobe, Japan.
 Meng, X., Temes, G.C. and Wang, T., “A LowPower ParasiticInsensitive SwitchedCapacitor Integrator for ΔΣ ADCs,” IEEE Internat. Circuits and Systems Symp., June 1 – 5, 2014, Melbourne, Australia.
 Meng, X., Li, W. and Temes, G.C. “A Fully Differential Input Amplifier With Bandpass Filter for Biosensors,” IEEE Internat. Circuits and Systems Symp., June 1 – 5, 2014, Melbourne, Australia.
 Zhang, Y., Chen, Ch., He, T. and Temes, G.C., “A ContinuousTime ΔΣ Modulator with a Digtal Technique for Excess Loop Delay Compensation,” IEEE Internat. Circuits and Systems Symp., June 1 – 5, 2014, Melbourne, Australia.
 Meng, X. and Temes, G.C., “Bootstrapping techniques for floating switches in switchedcapacitor circuits,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 36, 2014, College Station, TX
 Meng, X. and Temes, G.C., “Lowpower dutycycle tuned filters,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 36, 2014, College Station, TX.
 Meng, X. and Temes, G.C., “A noisecoupled lowdistortion deltasigma ADC with shifted loop delays,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 36, 2014, College Station, TX.
 Meng, X. and Temes, G.C., “Doublesampled wideband deltasigma ADC with shifted loop delays,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 36, 2014, College Station, TX.
 Payandehnia, P. et al., “Sequential interstage correlated double sampling,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 36, 2014, College Station, TX.
 Payandehnia, P. et al., “Multistep counting ADC,” IEEE Int’l Midwest Symp. on Circuits and Systems, Aug. 36, 2014, College Station, TX.
 Li, W., WangT., Grilo, J.A., and Temes,G.C. “A 0.45mW 12b 12.5MS/s SAR ADC with digital calibration,” IEEE Custom Integrated Circuits Conf., San Jose, CA, Sept. 15 – 17, 2014.
 Chen, CH, Zhang, Y., He, T., Chiang, P.Y. and Temes, G.C., “A 11µW 250 Hz BW twostep incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces,” IEEE Custom Integrated Circuits Conf., San Jose, CA, Sept. 15 – 17, 2014.
 Zhang, Y., Chen, CH, He, T. and Temes, G.C., “A 1 V, 59 fJ/Step, 15 MHz BW, 74 dB SNDR continuoustime ΔΣ modulator with digital ELD compensation and multibit FIR feedback,” IEEE Asian SolidState Circuits Conference, KaoHsiung, Taiwan, Nov. 1012, 2014.
 Chen, CH, He, T. and Temes, G.C., “Micropower incremental ADCs,” Proc. Advances in Analog Circuit Design (AACD) Workshop, invited, Neuchatel, Switzerland, April 2123, 2015, pp. 1 19.
 Payandehnia, P., Fazli, A., Meng, X., Yang, Chao and Temes, G.C., “A passive CMOs lowpass filter for high speed and high SNDR applications,” IEEE Internat. Circuits and Systems Symp., May 24  27, 2015, Lisbon, Portugal.
 He, T. Tao He, Yi Zhang, Xin Meng and Gabor Temes and Chiahung Chen, “MicroPower MultiStep Incremental ADCs for MultiChannel Sensor Interfaces,” IEEE Internat. Circuits and Systems Symp., May 24  27, 2015, Lisbon, Portugal.
 Sadollahi,M. and Temes, G., “Twostage ΔΣ ADC with noisecoupled VCObased quantizer,” IEEE Internat. Circuits and Systems Symp., May 24  27, 2015, Lisbon, Portugal.
 Meng, X., Zhang, Y., He, T., Payandehnia, P. and Temes, G.C., “A noisecoupled time interleaved ΔΣ modulator with shifted group delay,” IEEE Internat. Circuits and Systems Symp., May 24  27, 2015, Lisbon, Portugal.
 Meng, X. et al.,"A 19.2mW, 81.6dB SNDR, 4MHz Bandwidth DeltaSigma Modulator with Shifted Loop Delays," IEEE European SolidState Device Research & Circuits Conference, September 1418, 2015, Graz, Austria.
 Vahid Behravan, Shuo Li, Neil E. Glover, ChiaHung Chen, Mohammed Shoaib, Gabor C. Temes and Patrick Y. Chiang, “A CompressedSensing SensoronChip Incorporating Statistics Collection to Improve Reconstruction Performance,” IEEE Custom Integrated Circuits, Conf., San Jose, CA, Sept. 18 – 21, 2015.
 C.–H. Chen, Y. Zhang, T. He, and G. C. Temes, “An incremental analogtodigital converter with multistep extended counting for sensor interfaces,” IEEE Internat. Circuits and Systems Symp, 2016, Montreal, Canada, pp. 77 – 80.
 J. Cao and G. C. Temes, “Poweron Digital Calibration Method for DeltaSigma ADCs,” IEEE International Circuits and Systems Symp, 2016, pp.20022005.
 Zhang, Y., CH Chen, He, T. and G.C. Temes, “A 35 uW 96.8 dB SNDR 1 kHz BW multistep incremental ADC using multislope extended counting with a single integrator,” IEEE 2016 Symp. on VLSI Circuits, Honolulu, pp. 12.
 ChiaHung Chen, Yi Zhang, Gabor C. Temes, “History, present stateofart and future of incremental ADCs,” ESSCIRC European SolidState Circuits Conference, 2016, pp. 83–86.
 Zhang, Y.,CH Chen, He, T. and G.C. Temes, “A twocapacitor SARassisted multistep incremental ADC with a singleamplifier achieving 96.6 dB SNDR over 1.2 kHz BW,” IEEE Custom Integrated Circuits Conf., Austin, TX, Apr. 30 – May 3, 2017.
 He, T., Chen, CH., Zhang, Y. and Temes, G.C., “Incremental ADC with Parallel Counting,” IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, August 69, 2017.
 Sadollahi, M., Hamashita, K. Sobue, K. and Temes, G.C., “An 11bit 250 nW 10 kS/s SAR ADC with doubled input range for biomedical applications,” IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, August 69, 2017.
 Sadollahi, M., Hamashita, K. Sobue, K. and Temes, G.C., “Passive 3^{rd}order deltssigma ADC with VCObased quantizer,” IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, August 69, 2017.
 He, T., Kareppagoudr, M., Zhang, Y., Moon, U. and Temes, G.C., “Pseudopseudo differential circuits," IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, August 69, 2017.
Book Review
 Temes, G.C., Review of “Signals, Systems, and Networks,” by G. Fodor, IEEE Circuits and Systems Magazine, July 2003.
PATENTS
 “D.C. Bias Servomethod and Apparatus for Magnetic Recording Heads,” (with P. Bajka), U.S. Patent 3,564,160, February 1971.
 “Variable Sample Periodic Hold Electronic Delay Network,” U.S. Patent 3,587,007, June 1971.
 “Asymmetrical LossPole Mechanical Filter,” U.S. Patent 3,725,828, April 1973.
 “Photo Detector Input Circuit,” U.S. Patent 4,173,723, November 11, 1979.
 “Offset Compensated SwitchedCapacitor Circuits,” U.S. Patent 4,543,534, September 1985.
 “Pixel NonUniformity Correction System,” U.S. Patent, 4,602,291, July 1986.
 “Aktives Netzwerk,” West German Patent DE3401516C2, October 1986.
 “SwitchedCapacitor PseudoNPath Filter,” U.S. Patent 4,644,304, February 1987.
 “Pipelined DigitaltoAnalog Converter,” U.S. Patent 4,713,650, December 1987.
 “MultiStage SigmaDelta AnalogtoDigital Converter,” U.S. Patent 5,153,593, October 6, 1992.
 “HighOrder SigmaDelta AnalogtoDigital Converter,” U.S. Patent 5,198,817, March 30, 1993.
 “DualQuantization Oversampling DigitaltoAnalog Converter,” U.S. Patent 5,369,403, November 29, 1994.
 “TrackandHold Circuit Utilizing a Negative of the Input Signal for Tracking,” U.S. Patent 5,689,201, November 18, 1997.
 “Method and Apparatus for Use in SwitchedCapacitor Circuits,” U.S. Patent 6,873,278, March 29, 2005; European Patent Application, May 21, 2001.
 “SwitchedCapacitor Signal Scaling Circuit” U.S. Patent 7,046,046, Oct. 13, 2005.
Rev. 7/2017