## 2.1 Background Information

Arithmetic Logic Units (ALUs) are a critical component of processors, performing all integer arithmetic operations for the computer, while floating point operations are carried out in Floating Point Units (FPUs). Adders are used in ALUs to perform addition and subtraction, and are often used in other parts of the processor for other simple operations such as incrementing or decrementing numbers.

There are three main ways of implementing multi-bit adders using combinational logic: Ripple-Carry, Carry-Lookahead, and Carry-Save. The simplest method, and the method to be implemented in this section, is the ripple-carry adder. It is significantly slower than the other two options, but it has the benefit of being small, easy to understand, and easy to implement. Carry-Lookahead adders use some additional logic to speed up calculations, at the cost of increased size and complexity. Carry-Save adders are even faster, and even bigger than Carry-Lookahead adders.

Integrated circuit design often involves many tradeoffs that the designer must decide between. For instance, increasing speed will improve the circuit's performance, but the tradeoff is that increasing size also increases cost and power consumption. In some situations, a circuit designer may choose to use a slower implementation to keep cost and/or power consumption low.

## 2.2 Section Overview

Objective: Design and implement a 4-bit, ripple-carry adder using 8 switches for the inputs, and the LEDs on the FPGA to display the 5-bit output.

1. Create a block diagram for your design.
2. Fill out Table 2.1, the truth table for a full-adder.
3. Fill out Table 2.2, the partial truth table for a 4-bit adder.
4. Create a new project for this lab.
5. Create a schematic for a full-adder and generate symbol.
6. Implement 4 of your full-adder symbols in a new schematic, and connect them together to create a 4-bit adder.
7. Simulate the design of your 4-bit adder.
8. Program and test hardware.

## 2.3 Learning Objectives

In this section, the following items will be covered:

1. Creating block diagrams.
2. Creating and instantiating symbols in Quartus Prime schematics.
3. Simulating digital logic designs .

## 2.4 Materials

1. Quartus Prime Lite Edition V. 18.0
2. DE10-Lite kit with MAX10 10M50DAF484C7G FPGA
3. USB to USB-B cable
4. Chapter 5 of the textbook

## 2.5 Procedure

There are 6 steps to digital logic design: Figure 2.1: Use this process for designing the adder.

1. Design: The context of the design is established in this step. The context involves defining the inputs, desired outputs, and all the logic required in-between. In this step, all the minimizations and layout are planned for the design entry process. While this step is not always the longest, it should involve the most thought and effort. This typically requires a complete block diagram showing all the logic blocks and the connections between them, often with written explanations of specific functions.
2. Design Entry: The actual drafting of the digital logic design occurs in this step, translating the design from block diagrams and descriptions into the software. This can be accomplished directly by writing HDL code, or graphically by drawing a schematic that a software tool can convert into HDL code.
3. Design Simulation: Before committing to hardware, this step tests the design in a controlled computer simulation. If the design does not function as specified in the ”Design” step, it is revised.
4. Synthesize and Map Design: When the design simulates correctly, the HDL and schematic source files are synthesized into a design file that can be written to the FPGA. This includes assigning the inputs and outputs of the design to IO pins.
5. Program Hardware: After the design file is created, it is used to configure the FPGA. Quartus Prime sends a bit stream over the USB-B cable to configure the DE10-Lite FPGA.
6. Test Hardware: Verify hardware operation once the FPGA has been programmed. The FPGA should operate exactly as the design predicted, which was verified by the simulation. Synthesis problems, timing violations, or incorrect assumptions about the hardware can require the designer to return to the ”Design” step.

## 2.6 Design

### 2.6.1 Make a block diagram

Review section 1.5.2 for an overview of block diagrams.

Two example diagrams for this section are shown in Figure 2.2. The diagram on the left is a high-level description of the adder, showing the entire design as a single block with two 4-bit inputs and two outputs, Sum and Carry Out.  The inputs will be connected to switches and the outputs will be connected to LEDs. The diagram on the right side of Figure 2.2 shows how a four bit adder can be constructed using 4 full adders.  Note that the high level diagram is useful when you want to use a 4 bit adder in your project, but that a lower level diagram showing how to make this design out of full adders is more useful when trying to build a four bit adder with logic gates.

Follow these steps to create a complete block diagram from Figure 2.2:

1. This design will have one main block for the FPGA
2. Add three sub-blocks within the FPGA block:
1. Switches
2. Combinational Logic
3. LEDs
3. Show how the switches feed the Combinational Logic that connects to the LEDs within the FPGA.  Figure 2.2:  High level and low lever diagrams of a 4 bit adder

### 2.6.2 Make a functional truth table

Fill out the truth table below to describe the functionality of a full-adder. Four of these will be linked together to create a 4-bit, ripple-carry adder. A description of a full adder is shown at the beginning of Chapter 5 in the textbook.

 Operand1 + Operand2 + Carry In = Value (2-bit Binary) Value (Unsigned Decimal) 0b0 + 0b0 + 0b0 = 0b0 + 0b0 + 0b1 = 0b0 + 0b1 + 0b0 = 0b0 + 0b1 + 0b1 = 0b1 + 0b0 + 0b0 = 0b1 + 0b0 + 0b1 = 0b1 + 0b1 + 0b0 = 0b1 + 0b1 + 0b1 =

Table 2.1: Full-Adder Truth Table

Fill out the partial truth table below to describe the functionality of a 4-bit adder. Later in this section, you will compare this truth table to your simulation results to verify your design.

 Operand 1 + Operand 2 = Value (5-bit Binary) Value (Unsigned Decimal) Value (Hexadecimal) 0b0000 + 0b0000 = 0b0000 + 0b0001 = 0b0000 + 0b0010 = 0b0000 + 0b0011 = 0b0000 + 0b0100 = 0b0000 + 0b0101 = 0b1000 + 0b0000 = 0b1000 + 0b0001 = 0b1000 + 0b0010 = 0b1000 + 0b0011 = 0b1111 + 0b0011 = 0b1111 + 0b1000 = 0b1111 + 0b1010 = 0b1111 + 0b1011 =

Table 2.2: Partial 4-bit Adder Truth Table This table is incomplete; there are actually 256 (28) possible combinations! Complex designs can often be broken into several simple components, like you're doing here by building a 4-bit adder (256 IO combinations) out of 4 full-adders (8 IO combinations each).

### 2.6.3 Design the Logic

In the next lab you will learn to go from a truth table to logic gates using Karnaugh Maps (Section 2.7.2 of Textbook). For this lab, the Full adder Logic is given to you in Sum of Products Form (Section 2.2.2 of Textbook)

SUM = A ⊕ B ⊕ Cin

Cout = AB + ACin + BCin

Read the Textbook for more information about this form of writing logic and how it is generated. In short, things added together are OR gated together, things multiplied are AND gated together. ⊕ is XOR. Follow the Order of opperations.

## 2.7 Design Entry

1. Create a new Project in Quartus, make two shematic files, and enter the full-adder design the schematic file that is not the top Level. Be sure to label the inputs and outputs in this schematic! Refer back to Section 1.6 for instructions on how to create a new project and add schematic files.
2. Generate a symbol from the full-adder schematic by selecting File→ Create/Update →Create Symbol file for current file. This will add a new symbol into the [Project] library of the Symbol menu in the schematic editor.
3. In the Top level file instantiate that symbol 4 times, then connect those full-adders together to create a 4-bit adder.
4. Label the 4-bit number inputs A0-A3 and B0-B3 and outputs Z0-Z4, with 0 being the least-significant bit, and 3 being the most-significant.
5. Label the carry-in input to the least-significant full-adder. Connect this to a switch or push button.  Note that Key0 and Key1 are active low devices.  They output a 1 when not pushed and a 0 when pushed.

## 2.8 Design Simulation

Simulation is done with modlesim for this course. See the links of the main page of the lab website for information on the software.

To genereate the Verilog file neccicary to use modelsim, go to File -> create/update -> create HDL Design File for current file -> Verilog

This is a hardware description language (HDL) file. Open it in Modelsim and simulate your design.

Simulation is not required for Section 2 if you have the FPGA. If you do not have the FPGA, Simulation will be used for design validation for checkoff.

## 2.9 Synthesize and Map Design

Follow the same process for using Spreadsheet view as in Section 1.8.

## 2.10 Program Hardware

Program the DE10-Lite using the same process as in Section 1.9.

## 2.11 Test Design

Validate that the design performs according to Table 2.2.

## 2.12 Checkoff

• Table 2.1 filled out
• Table 2.2 filled out
• Hardware or simulation output matches tables

## 2.13 Study Questions

The study questions go at the end of the Lab Report

1. Explain how you would convert your 4-bit adder to a 4-bit adder/subtractor.
2. Explain your what you did with the least-significant full-adder's carry-in. Why?

## 2.14 Challenge - Extra Credit

This section designed, built, and tested (simulation and hardware validation) a simple 4-bit adder. Now, modify your design to include a 9th input control pin  (Information on ALUs can be found in chapter 5 in your textbook). Full credit will be given for design, simulation, and implementation onto the FPGA.

1. Control pin low: (Operand 1) + (Operand 2)
2. Control high: (Operand 1) - (Operand 2)