7.1 Background Information

Early video game consoles developed in the mid 80's leveraged sprites to display images that would shift and move around the screen.  This lab will use the VGA controller developed in the prior section of lab to display a sprite on the screen.

7.2 Section Overview

Objective: Design a system that will load image data into memory and then display that image correctly on a screen.  If a VGA screen is not available, this lab can be checked off by completing the simulation of your system in ModelSim.

  • Select an image and initailize the Memory Initialization File (MIF)
  • Modify your prior lab to output the necessary values, such as row and column currently being displayed.
  • Create a memory address converter that translates the row and column to an index of the memory block.
  • Program and test hardware.

7.3 Learning Objectives

  1. Learn about memory.
  2. Learn about how images are displayed as an array of pixels.

7.4 Materials

  1. Quartus Prime Lite Edition V. 18.0
  2. DE10-Lite kit with MAX10 10M50DAF484C7G FPGA
  3. USB to USB-B cable

7.5 Procedure:

There are 6 steps to digital logic design

Design Process Figure 7.1: Use this process for designing the final project.

  1. Design: The context of the design is established in this step. The context involves defining the inputs, desired outputs, and all the logic required in-between. In this step, all the minimizations and layout are planned for the design entry process. While this step is not always the longest, it should involve the most thought and effort. This typically requires a complete block diagram showing all the logic blocks and the connections between them, often with written explanations of specific functions.
  2. Design Entry: The actual drafting of the digital logic design occurs in this step, translating the design from block diagrams and descriptions into the software. This can be accomplished directly by writing HDL code, or graphically by drawing a schematic that a software tool can convert into HDL code.
  3. Design Simulation: Before committing to hardware, this step tests the design in a controlled computer simulation. If the design does not function as specified in the ”Design” step, it is revised.
  4. Synthesize and Map Design: When the design simulates correctly, the HDL and schematic source files are synthesized into a design file that can be written to the FPGA. This includes assigning the inputs and outputs of the design to IO pins.
  5. Program Hardware: After the design file is created, it is used to configure the FPGA. Quartus Prime sends a bit stream over the USB-B cable to configure the DE10-Lite FPGA.
  6. Test Hardware: Verify hardware operation once the FPGA has been programmed. The FPGA should operate exactly as the design predicted, which was verified by the simulation. Synthesis problems, timing violations, or incorrect assumptions about the hardware can require the designer to return to the ”Design” step.

7.6 Design

Lab7 Structure
Figure 8:  The general structure for using lab 6 to display an image on the VGA screen.

Displaying an image on a VGA monitor requires several tasks be completed.  First the lab 6, VGA display driver, may need to be modified to output the row and column being displayed at that given time.  The row and column are then used to determine if the sprite is being displayed or if the background color is displayed.  Finally the row and column are used by an address converter to select a specific cell of the ROM, which contains the RGB values for the displayed image.  The ROM needs to be initialized with a memory initialization file (.mif).  The prelab has a link to a github created by the TAs which will help convert an image into the necessary format.  ModelSim is very important for verifying operation and connection of these blocks.

7.7 Design Entry

No inputs are needed for this lab.  Just display a sprite on the VGA output of the FPGA. Transcribe your block diagrams and logic into SystemVerilog.

7.8 Design Simulation

It is highly recommended that use use ModelSim to simulate your design.

7.9 Test Hardware

Program the DE10_Lite and test the VGA output with a monitor.

7.10 Checkoff

  • A software-level block diagram.

  • A proper System Verilog Implementation of the Sync module.

  • Valid hardware output or a thorough ModelSim simulation that demonstrates functionality of your project.

7.11 Study Questions

1. What was the toughest aspect of ECE 272? What should be changed or added to the ECE 272 manual to make this course better?
2. What would you like to explore further about Quartus Prime or Digital Logic Design?
3. What section of ECE 272 did you dislike the most? Why?
4. What was your favorite section of ECE 272? Why?

7.12 Challenge

Draw the clock from lab 5 on the screen.  Use sprites to display numbers for hours, minutes, and seconds.