OREGON STATE UNIVERSITY

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2012
Ferriss, M. A., J-O. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, S. Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno, et al., "An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS", 2012 IEEE Symposium on VLSI Circuits2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, IEEE, pp. 176 - 177, 06/2012.