Biblio

Found 14 results

2012
Jiang, T., P. Y. Chiang, and K. Hu, "A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing", 2012 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, IEEE, pp. 1 - 4, 04/2012. Abstract
2011
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Hu, K., T. Jiang, S. Palermo, and P. Y. Chiang, "Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS", IEEE Custom Integrated Circuits Conference - CICC 2011, San Jose, CA, IEEE, pp. 1 - 4, 09/2011. Abstract
2010
Jiang, T., W. Liu, F. Y. Zhong, C. Zhong, and P. Y. Chiang, "Single-Channel, 1.25-GS/s, 6-Bit, Loop-Unrolled Asynchronous SAR-ADC in 40nm-CMOS", 2010 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 1 - 4, 09/2010. Abstract
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Jiang, T., and P. Y. Chiang, "Energy-efficient, decision feedback equalization Using SAR-like capacitive charge summation", 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsin Chu, Taiwan, IEEE, pp. 249 - 252, 04/2010. Abstract
2009
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Hu, K., T. Jiang, and P. Y. Chiang, "Comparison of on-die global clock distribution methods for parallel serial links", IEEE International Symposium on Circuits and Systems - ISCAS 2009, Taipei, Taiwan, IEEE, pp. 1843 - 1846, 05/2009. Abstract
, , , 05/2009.
Jiang, T., and P. Y. Chiang, "Sense amplifier power and delay characterization for operation under low-Vdd and low-voltage clock swing", IEEE International Symposium on Circuits and Systems - ISCAS 2009, Taipei, Taiwan, IEEE, pp. 181 - 184, 05/2009. Abstract