Monday, April 10, 2017 - 4:00pm to 4:50pm
LPSC 125

Speaker Information

Tawfiq Musah
research scientist
PHY Research Lab, Intel Corporation, OR

Abstract

As bandwidth demand for off-chip interconnect continues to increase, optimizing I/O energy efficiency is essential for computing platforms ranging from handheld devices to high-end data centers. Many server and desktop platforms contain conventional board and packaging topologies that have been used for decades. Complex equalizers are therefore required to signal across these channels at high rates. This has resulted in steep trade-offs between scaling I/O rates and maintaining high energy-efficiency. This presentation will highlight design challenges to scaling multi-Gb/s I/O beyond 10Gb/s, and use a data-rate scalable bidirectional link design to showcase circuit and system techniques to overcome these challenges. The role of ADC/DSP-based I/O design approach in enabling the next generation of energy-efficient links will also be discussed.

Speaker Bio

Tawfiq Musah is a research scientist at the PHY Research Lab, Intel Corporation, OR. His work focuses on modeling and design of circuits and systems to enable Intel's next generation chip-to-chip electrical and optical links. Dr. Musah received the B.S. degree in electrical engineering from Columbia University, NY, in 2005 and the Ph.D. degree in electrical and computer engineering from Oregon State University, OR, in 2010. Before joining Intel in 2010, he interned at Texas Instruments designing a hardware sensor in 2010 and Intel Labs working on micro-power ADC in 2006 and 2007. He is a recipient of Intel Lab Divisional Recognition Award in 2014 and Intel Labs Academy Award for Excellence in Bringing New Experiences or Technical Innovation to Market in 2015.