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A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application

TitleA double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application
Publication TypeConference Paper
Year of Publication2011
AuthorsLee, S., J. Chae, M. Aniya, S. Takeuchi, K. Hamashita, P K. Hanumolu, and G. C. Temes
Conference Name2011 IEEE Custom Integrated Circuits Conference (CICC)
Pagination1 - 4
Date Published09/2011
PublisherIEEE
Conference LocationSan Jose, CA
ISBN Number978-1-4577-0222-8
Abstract

A cascade switched-capacitor ΔΣ analog-to-digital converter, suitable for WLANs, is presented. It uses a double-sampling scheme with single set of DAC capacitors, and an improved low-distortion architecture with an embedded-adder integrator. The proposed architecture eliminates one active stage, and reduces the output swings in the loop-filter and hence the non-linearity. It was fabricated with a 0.18um CMOS process. The prototype chip achieves 75.5 dB DR, 74 dB SNR, 73.8 dB SNDR, -88.1 dB THD, and 90.2 dB SFDR over a 10 MHz signal band with an FoM of 0.27 pJ/conv-step.

DOI10.1109/CICC.2011.6055289