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A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer

TitleA 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer
Publication TypeConference Paper
Year of Publication2010
AuthorsChae, J., S. Lee, M. Aniya, S. Takeuchi, K. Hamashita, P K. Hanumolu, and G. C. Temes
Conference Name2010 IEEE Custom Integrated Circuits Conference 2010
Pagination1 - 4
Date Published09/2010
PublisherIEEE
Conference LocationSan Jose, CA
ISBN Number978-1-4244-5758-8
Abstract

A wideband ΔΣ ADC using a novel double-sampling scheme with a single set of capacitors and a dynamic embedded-adder quantizer is presented. The proposed quantizer eliminates static currents in the adder of a low-distortion architecture. Fabricated in 0.18 μm CMOS process, the prototype chip operates with a 320 MHz sampling frequency and achieves 63 dB SNDR in a 20 MHz signal band while consuming 16 mW power.

DOI10.1109/CICC.2010.5617594