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A 250 mV, 352 uW GPS Receiver RF Front-Eng in 130nm CMOS

TitleA 250 mV, 352 uW GPS Receiver RF Front-Eng in 130nm CMOS
Publication TypeJournal Article
Year of Publication2011
AuthorsHeiberg, A. C., T. W. Brown, T. S. Fiez, and K. Mayaram
JournalIEEE Journal of Solid-State Circuits
Pagination938 - 949
Date Published04/2011
KeywordsGPS, LNA, low voltage, mixer, quadrature, receiver, RF front-end, subthreshold, VCO

A fully integrated CMOS GPS receiver RF front-end is presented. Systematic circuit optimizations for ultra-low voltage operation including subthreshold biasing, a novel mixer-VCO interface, and charge neutralization enable the supply voltage to be dramatically reduced as a means to save power. The 250 mV supply is the lowest ever reported for any integrated receiver RF front-end to date. Its 352 μW power consumption represents a three times power savings compared to the prior lowest GPS receiver RF front-ends reported in the literature. The prototype was fabricated in a 1P8M 130 nm CMOS process and includes a variable gain LNA, a quadrature VCO, quadrature mixers, and all required bias circuitry. The system has a measured gain of 42 dB, a noise figure of 7.2 dB, and an oscillator phase noise of - 112.4 dBc/Hz at a 1 MHz offset, resulting in a VCO FoM of 187.4 dBc/Hz.

Short TitleIEEE J. Solid-State Circuits