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A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

TitleA Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations
Publication TypeJournal Article
Year of Publication2012
AuthorsPostman, J., and P. Y. Chiang
JournalISRN Electronics
Volume2012891543625
Issue424170
Pagination1 - 9
Date Published2012
Abstract

Scaling CMOS process technology continues to enable increased levels of system integration, leading to on-chip communication demands beyond what traditional digital signaling techniques can efficiently provide with sufficient reliability. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, energy, and reliability and provide a review of interconnect reliability considerations. Finally, we provide a case study to evaluate the efficiency of error correcting codes on a state-of-the-art energy-efficient low-swing interconnect.

DOI10.5402/2012/916259
Short TitleISRN Electronics