Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits

TitleSub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits
Publication TypeJournal Article
Year of Publication2012
AuthorsXia, L., J. Wang, W. Beattie, J. Postman, and P. Y. Chiang
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue2
Pagination276 - 284
Date Published02/2012
ISSN1558-0806
Keywordshistogram counter, multi-phase, time-interleaved, timing error calibration
Abstract

A foreground digital calibration method is presented that calibrates the timing offsets between the multiple T/H (track/hold) circuits of time-interleaved analog-to-digital converters and multi-phase serial links. Two quantizer-based phase detectors sample the outputs of adjacent track/hold circuits, detecting any phase offsets arising from process mismatches in both the timing verniers and the T/H switches, and store the resulting digital decisions in histogram counters. Measurement inaccuracies resulting from quantizer offset are averaged away statistically by a round-robin rotation of the dual samplers, compensating for comparator imprecision. Built in a 90-nm CMOS process, the proposed calibration technique, after three iterations of both the phase measurement and subsequent timing vernier adjustment, reduces the static phase offset of each channel to less than ±0.5 ps in an 8-channel, 8 GS/s time-interleaved system. Further measurements using a T/H circuit as a down-conversion mixer confirm a residual phase error of less than ±2 ps.

DOI10.1109/TCSI.2011.2162382
Short TitleIEEE Trans. Circuits Syst. I
Refereed DesignationRefereed