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A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI

TitleA 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI
Publication TypeConference Paper
Year of Publication2012
AuthorsPawlowski, R., E. Krimer, J. Crop, J. Postman, N. Moezzi-Madani, M. Erez, and P. Y. Chiang
Conference Name2012 IEEE International Solid- State Circuits Conference - (ISSCC
Pagination492 - 494
Date Published02/2012
PublisherIEEE
Conference LocationSan Francisco, CA
ISBN Number978-1-4673-0375-0
Abstract

Near-threshold computing exhibits improved energy efficiency compared to nominal super-threshold operation [1, 2]. Two critical bottlenecks prevent mainstream adoption of low-VDD operation: degraded logic delay resulting in significantly lower throughput than at super-threshold, and excessive, unpredictable delay variation caused by increased sensitivity to process and dynamic variations.

DOI10.1109/ISSCC.2012.6177105