OREGON STATE UNIVERSITY

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A 12.5-bit 4 MHz 13.8 mW MASH Delta-Sigma Modulator With Multirated VCO-Based ADC

TitleA 12.5-bit 4 MHz 13.8 mW MASH Delta-Sigma Modulator With Multirated VCO-Based ADC
Publication TypeJournal Article
Year of Publication2012
AuthorsAsl, S Z., S. Saxena, P K. Hanumolu, K. Mayaram, and T. S. Fiez
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue8
Pagination1604 - 1613
Date Published08/2012
ISSN1558-0806
Abstract

A novel MASH delta-sigma (ΔΣ) ADC architecture is introduced that has a multirated voltage controlled oscillator (VCO)-based ADC in its second stage. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. A prototype consists of a first-order switched-capacitor (SC) modulator operating at 100 MHz in the first stage followed by a second-stage VCO-based ADC operating at 1.2 GHz. A custom IC prototype of this architecture achieves 77.3 dB signal-to-noise-ratio (SNR) over a 4 MHz signal bandwidth with a power consumption of 13.8 mW. It was fabricated in a 130 nm 1P8M CMOS process. The resulting FoM is 298 fJ per conversion.

DOI10.1109/TCSI.2012.2206506
Short TitleIEEE Trans. Circuits Syst. I