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Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End

TitleHighly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End
Publication TypeJournal Article
Year of Publication2013
AuthorsRajaee, O., and U. Moon
JournalIEEE Journal of Solid-State Circuits
Volume48
Issue2
Pagination502 - 515
Date Published02/2013
ISSN1558-173X
Abstract

A noise-shaped pipelined ADC is presented in this paper. A minimal complexity ΔΣ modulator in the first two sub-ADCs and residue feedback in the latter stages lead to high-order noise shaping. This also leads to reduced sensitivity to analog imperfections in the front-end stage. Implemented in 0.18- μm CMOS, the ADC achieves 12 ENOB with 64-MHz clock at 6× OSR while using only a 9-b linear front-end multiplying DAC. The delta-sigma sub-ADCs dissipate 400 μW of extra power (out of 13.9-mW total power) while significantly enhancing the overall ADC linearity.

DOI10.1109/JSSC.2012.2227605
Short TitleIEEE J. Solid-State Circuits