OREGON STATE UNIVERSITY

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Electrical Modeling of Thin-Film Transistors

TitleElectrical Modeling of Thin-Film Transistors
Publication TypeJournal Article
Year of Publication2008
AuthorsHong, D., G. Yerubandi, H. Q. Chiang, M. C. Spiegelberg, and J. F. Wager
JournalCritical Reviews in Solid State and Materials Sciences
Volume33
Issue2
Pagination101 - 132
Date Published4/2008
ISSN1040-8436
Keywords3-layer model, channel mobility, comprehensive depletion-mode model, conductance integral equation, device modeling, discrete trap model, fringing current artifacts, series resistance, square-law model, thin-film transistors, trapping
Abstract

An overview of device physics-oriented electrical modeling of thin-film transistors (TFTs) is presented. Four specific models are considered: (i) square-law, (ii) 3-layer, (iii) comprehensive depletion-mode, and (iv) discrete trap. For each model, a functional assessment of model equations is undertaken in terms of independent and dependent variables, model parameters, physical operating parameters, and constraining inequalities in order to facilitate mapping of model equations into a corresponding equivalent circuit. Channel mobility and “subthreshold” current trends are elucidated. Finally, a conductance integral equation based on Shockley's gradual channel approximation is introduced and is employed in model development and device assessment.

DOI10.1080/10408430701384808
Short TitleCritical Revs. in Solid State & Mat. Sc.BSMS