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Conference Program
Monday, October 16
8:30-9:15 Continental Breakfast 9:15-9:30 Welcome Ali Hurson (Conference Chair) and Mary Lou Soffa (Program Chair) 9:30-10:30 Keynote Speaker Fred Pollack, Intel Corporation
New Challenges in Microarchitecture and Compiler Design10:30-11:00 Break 11:00-12:30 Session 1: Register Allocation and Analysis - Session Chair: Kemal Ebcioglu 11:00-11:30 Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining
by Mikhail Smelyanski, Gary Tyson and Edward Davidson (University of Michigan)11:30-12:00 Global Register Partitioning
by Jason Hiser (University of Virginia), Steve Carr and Philip Sweany (Michigan Technological University)12:00-12:30 Region Formation Analysis with Demand-driven Inlining for Region-Based Optimization
by Tom Way, Ben Breech and Lori Pollock (University of Delaware)12:30-2:00 Lunch 2:00-3:30 Session 2: Architectural Design - Session Chair: Skevos Evripidou 2:00-2:30 aSOC: A Scalable, Single-Chip Communication Architecture
by Jian Liang, Sriram Swaminathan, and Russell Tessier (University of Massachusetts)2:30-3:00 Address Partitioning in DSM Clusters with Parallel Coherence Controllers
by Ilanthiraiyan Pragaspathy and Babak Falsafi (Purdue University)3:00-3:30 Custom Wide Counterflow Pipelines for High-Performance Embedded Applications
by Bruce R. Childers (University of Pittsburgh) and Jack W. Davidson (University of Virginia)3:30-4:00 Break 4:00-5:40 Session 3: Optimizations and Opportunities - Session Chair: Evelyn Duesterwald 4:00-4:30 A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization
by Kim M. Hazelwood and Thomas M. Conte (North Carolina State University)4:30-5:00 Exploring the Limits of Sub-word Level Parallelism
by Kevin Scott and Jack Davidson (University of Virginia)5:00-5:20 The Dynamic Trace Memorization Reuse Technique
by Amarildo da Costa, Felipe Franca and Eliseu Filho (University of Rio de Janeiro, Brazil)5:20-5:40 Exploring Sub-block Value Reuse for Superscalar Processors
by Jian Huang (Sun Microsystems) and David Lilja (University of Minnesota)6:30-7:30 Reception
Tuesday, October 17
8:30-9:00 Continental Breakfast 9:00-10:00 Keynote Speaker Michael Smith, Harvard University
Dynamic Optimization: An Online Opportunity10:00-10:30 Break 10:30-12:00 Session 4: High Performance Memory Techniques - Session Chair: David O'Hallaron 10:30-11:00 Hiding Relaxed Memory Consistency with Compilers
by Jaejin Lee (Michigan State University) and David A. Padua (University of Illinois at Urbana-Champaign)11:00-11:30 Neighborhood Prefetching on Multiprocessors Using Instruction History
by David Koppelman (Louisiana State University)11:30-12:00 Characterization of Silent Stores
by Gordon Bell, Kevin M. Lepak and Mikko H.Lipasti (University of Wisconsin)12:00-2:00 Lunch 2:00-3:20 Session 5: Speculation and Prediction - Session Chair: Jim Dehnert 2:00-2:30 On Some Implementation Issues for Value Prediction on Wide-Issue Processors
by Sang-Jeong Lee (Soonchunhyang University, Korea) and Pen-Chung Yew (University of Minnesota)2:30-3:00 A Unified Compiler Framework for Control and Data Speculation
by Roy Dz-ching Ju (Intel Corporation), Kevin Nomura (Network Applications), Uma Mahadevan and Le-Chun Wu (Hewlett-Packard Company)3:00-3:20 Applying Data Speculation in Modulo Scheduled Loops
by Uma Mahadevan (Hewlett Packard Company), Kevin Nomura (Network Applications), Roy Dz-ching Ju (Intel Corporation) and Rick Hank (Hewlett Packard Company)3:20-4:00 Break 4:00-5:40 Session 6: Branch Prediction - Session Chair: Sally McKee 4:00-4:30 Branch Prediction in Multi-Threaded Processors
by Jayanth Gummaraju and Manoj Franklin (University of Maryland)4:30-5:00 The Effect of Code Reordering on Branch Prediction
by Alex Ramirez, Josep L. Larriba-Pey and Mateo Valero (Universitat Politecnica de Catalunya, Spain)5:00-5:20 A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions
by Kevin Skadron (University of Virginia), Margaret Martonosi and Douglas W. Clark (Princeton University)5:20-5:40 Dynamic Branch Prediciton for a VLIW Processor
by J. Hoogerbrugge (Phillips Research Laboratories, the Netherlands)
Wednesday, October 18
8:30-9:00 Continental Breakfast 9:00-10:00 Keynote Speaker Monty Denneau, IBM T.J. Watson Research Center
Blue Gene10:00-10:30 Break 10:30-12:00 Session 7: Parallel Computation - Session Chair: Guang Gao 10:30-11:00 Fine Grained Multithreading with Process Calculi
by Luis Lopes, F. Silva and V. Vasconcelos (University of Porto, Portugal)11:00-11:30 Data Relation Vectors: A New Abstraction for Data Optimizations
by Mahmut Kandemir (Pennsylvania State University) and J. Ramanujam (Louisiana State University)11:30-12:00 Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation
by T. Kisuki and P.M.W. Knijnenburg (Leiden University, The Netherlands) and M.F.P. O'Boyle (Edinburgh University, UK)12:00-1:30 Lunch 1:30-2:50 Session 8: Applications - Session Chair: Lori Pollock 1:30-2:00 Faster FFTs via Architecture-Cognizance
by Kang Su Gatlin and Larry Carter (University of California San Diego)2:00-2:30 Hybrid Parallel Circuit Simulation Approaches
by Edwin Naroska (University of Dortmund), Rung-Ji Shang and Feipei Lai (National Taiwan University), and Uwe Schwiegelshohn (University of Dortmund)2:30-2:50 Multithreaded programming of PC clusters
by Martin Schulz (Technische Universitat Munchen)2:50-3:15 Break 3:15-4:35 Session 9: Instruction Scheduling - Session Chair: David Kaeli 3:15-3:45 A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Processors
by Hui Wu, Joxan Jaffar and R. Yap (National University of Singapore)3:45-4:15 Instruction Scheduling for Clustered VLIW DSPs
by Rainer Leupers (University of Dortmund)4:15-4:35 Efficient Backtracking Instruction Schedulers
by Santosh G. Abraham (Hewlett-Packard Laboratories), Waleed M. Meleis and Ivan D.Baev (Northeastern University)
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