Patrick Chiang

Associate Professor
Electrical & Computer Engineering
Education: 
  • University of California - Berkeley,  B.S. Degree, 1998, Electrical Engineering
  • Stanford University, M.S. Degree, 2001, Electrical Engineering
  • Stanford University, Ph.D., 2007, Electrical Engineering
Biography: 

Patrick Chiang received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 2001 and 2007.

In 1998, he was with Datapath Systems (now LSI Logic), working on analog front-ends for DSL chipsets. In 2002 he was a research intern at Velio Communications (now Rambus) working on 10GHz clock synthesis architectures. In 2004 he was a consultant at startup Telegent Systems, evaluating low phase noise VCOs for CMOS mobile TV tuners. In 2006 he was a visiting NSF postdoctoral researcher at Tsinghua University, China, investigating low power, low voltage RF transceivers. In 2009 he was a visiting senior researcher at the ASIC State & Key Laboratory in Fudan University, Shanghai, China.

His interests are: 1) The design of energy-efficient, CMOS interconnects (on-chip/off-chip/wireless) — Energy-efficient interfaces will soon be a dominant portion of the power budget on future microprocessors and SoCs. These include on-chip links, off-chip multi-gigahertz I/O, and wireless data transmission. We are investigating new techniques in advanced CMOS processes to enable improved energy-efficiency (pJ/bit-transferred).

2) Wireless, wearable medical sensors — Advances in semiconductor technology will soon enable “bandaid-size” medical sensors, non-invasively attached to the human body, allowing for non-invasive monitoring of human activity. These sensors will capture measurement of minute electrical signals (i.e. brain-EEG signals, heart-ECG waves, accelerometer-based activity monitoring), which will provide continuous monitoring of medical condition, such as disease onset, vitamin/drug efficacy, sleep diagnosis, and brain cognition.

Research Interests: 

Research Areas
Energy-efficient CMOS interconnects (gigahertz ADCs, wireline on/off chip I/O, wireless); Wireless medical electronics

2013
2012
Postman, J., and P. Y. Chiang, "A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations", ISRN Electronics, vol. 2012891543625, issue 424170, pp. 1 - 9, 2012. Abstract
Pu, X., L. Wan, Y. Sheng, P. Y. Chiang, Y. Qin, and Z. Hong, "A wireless 8-channel ECG biopotential acquisition system for dry electrodes", 2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Singapore, Singapore, IEEE, pp. 140 - 142, 11/2012. Abstract
Luo, Y., C. Winstead, and P. Y. Chiang, "125Mbps ultra-wideband system evaluation for cortical implant devices", 2012 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), San Diego, CA, IEEE, pp. 779 - 782, 09/2012. Abstract
Morton, T., A. Weeks, S. House, P. Y. Chiang, and C. Scaffidi, "Location and activity tracking with the cloud", 2012 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), San Diego, CA, IEEE, pp. 5846 - 5849, 09/2012. Abstract
Morton, T., A. Weeks, S. House, P. Y. Chiang, and C. Scaffidi, "Location and activity tracking with the cloud", 2012 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), San Diego, CA, IEEE, pp. 5846 - 5849, 09/2012. Abstract
Cheng, J., L. Xia, C. Ma, Y. Lian, X. Xu, P. C. Yue, Z. Hong, and P. Y. Chiang, "A near-threshold, multi-node, wireless body area sensor network powered by RF energy harvesting", 2012 IEEE Custom Integrated Circuits Conference - CICC 2012, San Jose, CA, IEEE, pp. 1 - 4, 09/2012. Abstract

Best poster award.

Moezzi-Madani, N., T. Thorolfsson, P. Y. Chiang, and W. R. Davis, "Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding", Journal of Signal Processing Systems, vol. 68, issue 2, pp. 171 - 182, 08/2012. Abstract
Qi, N., Y. Xu, B. Chi, Y. Xu, X. Yu, X. Zhang, N. Xu, P. Y. Chiang, W. Rhee, and Z. Wang, "A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, issue 8, pp. 1720 - 1732, 08/2012. Abstract
Donkoh, E., and P. Y. Chiang, "A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability", Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, Redondo Beach, CA, ACM, pp. 155–160, 08/2012.
Donkoh, E., T. S. Ong, Y. N. Too, and P. Y. Chiang, "Register file write data gating techniques and break-even analysis model", Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, Redondo Beach, CA, ACM, pp. 149–154, 08/2012. Abstract
Postman, J., T. Krishna, C. Edmonds, L. - S. Peh, and P. Y. Chiang, "SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, issue 99, pp. 1 - 1, 08/2012. Abstract
Xia, L., C. Hu, S. Redfield, S. Woracheewan, R. Khanna, J. Nejedlo, H. Liu, and P. Y. Chiang, "Wireless Interconnects for Future Computing Systems", Intel ® Technology Journal, vol. 16, issue 2, pp. 134-155, 08/2012. Abstract
Hu, K., L. Wu, and P. Y. Chiang, "A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, issue 7, pp. 1336 - 1341, 07/2012. Abstract
Krimer, E., P. Y. Chiang, and M. Erez, "Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures", Proceedings of the 39th Annual International Symposium on Computer Architecture , vol. 40, issue 3, Portland, OR, pp. 237-248 , 06/2012. Abstract
Crop, J., R. Pawlowski, and P. Y. Chiang, "Regaining throughput using completion detection for error-resilient, near-threshold logic", Proceedings of the 49th Annual Design Automation Conference - DAC '12, San Francisco, CA, ACM Press, pp. 974-979, 06/2012. Abstract
Chen, C. - H., J. Crop, J. Chae, P. Y. Chiang, and G. C. Temes, "A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits", 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012, Seoul, Korea (South), IEEE, pp. 2969 - 2972, 05/2012. Abstract
Jiang, T., P. Y. Chiang, and K. Hu, "A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing", 2012 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, IEEE, pp. 1 - 4, 04/2012. Abstract
Pawlowski, R., E. Krimer, J. Crop, J. Postman, N. Moezzi-Madani, M. Erez, and P. Y. Chiang, "A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI", 2012 IEEE International Solid- State Circuits Conference - (ISSCC, San Francisco, CA, IEEE, pp. 492 - 494, 02/2012. Abstract
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