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Li, C., R. Bai, A. Shafik, E. Z. Tabasy, G. Tang, C. Ma, C. - H. Chen, Z. Peng, M. Fiorentino, P. Y. Chiang, et al., "A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver", 2013 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 124 - 125, 02/2013.
Postman, J., and P. Y. Chiang, "A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations", ISRN Electronics, vol. 2012891543625, issue 424170, pp. 1 - 9, 2012.
Luo, Y., C. Winstead, and P. Y. Chiang, "125Mbps ultra-wideband system evaluation for cortical implant devices", 2012 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), San Diego, CA, IEEE, pp. 779 - 782, 09/2012.
Moezzi-Madani, N., T. Thorolfsson, P. Y. Chiang, and W. R. Davis, "Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding", Journal of Signal Processing Systems, vol. 68, issue 2, pp. 171 - 182, 08/2012.
Qi, N., Y. Xu, B. Chi, Y. Xu, X. Yu, X. Zhang, N. Xu, P. Y. Chiang, W. Rhee, and Z. Wang, "A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, issue 8, pp. 1720 - 1732, 08/2012.
Donkoh, E., and P. Y. Chiang, "A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability", Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, Redondo Beach, CA, ACM, pp. 155–160, 08/2012.
Donkoh, E., T. S. Ong, Y. N. Too, and P. Y. Chiang, "Register file write data gating techniques and break-even analysis model", Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, Redondo Beach, CA, ACM, pp. 149–154, 08/2012.
Hu, K., L. Wu, and P. Y. Chiang, "A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, issue 7, pp. 1336 - 1341, 07/2012.
Krimer, E., P. Y. Chiang, and M. Erez, "Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures", Proceedings of the 39th Annual International Symposium on Computer Architecture , vol. 40, issue 3, Portland, OR, pp. 237-248 , 06/2012.
Crop, J., R. Pawlowski, and P. Y. Chiang, "Regaining throughput using completion detection for error-resilient, near-threshold logic", Proceedings of the 49th Annual Design Automation Conference - DAC '12, San Francisco, CA, ACM Press, pp. 974-979, 06/2012.
Jiang, T., P. Y. Chiang, and K. Hu, "A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing", 2012 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, IEEE, pp. 1 - 4, 04/2012.
Xia, L., J. Wang, W. Beattie, J. Postman, and P. Y. Chiang, "Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, issue 2, pp. 276 - 284, 02/2012.